公开(公告)号：US20240371905A1

公开(公告)日：2024-11-07

申请号：US18309933

申请日：2023-05-01

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Swarnal BORTHAKUR ,  Marc Allen SULFRIDGE ,  Jeffrey Peter GAMBINO ,  Vladimir KOROBOV ,  Richard MAURITZSON ,  David T. PRICE

IPC: H01L27/146 ,  H01L23/58

Abstract: A semiconductor device may include a first chip that includes a first wafer and a first dielectric layer disposed thereon. The semiconductor device may include a second chip that includes a second wafer and a second dielectric layer disposed thereon, the second chip having a backside surface and a frontside surface opposed to the backside surface, the second chip being bonded to the first chip at the frontside surface to define a bond line between the first dielectric layer and the second dielectric layer. An opening through the backside surface of the second chip may extend into the second dielectric layer, and a bond pad may be disposed within the second dielectric layer between the second wafer and the bond line.

公开(公告)号：US12131981B2

公开(公告)日：2024-10-29

申请号：US18357931

申请日：2023-07-24

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yushuang Yao ,  Vemmond Jeng Hung Ng

IPC: H01L23/492 ,  H01L21/48

CPC classification number: H01L23/4924 ,  H01L21/4871

Abstract: Implementations described herein are related to a semiconductor device package having an improved baseplate. In such an improved baseplate, there is a recess cut out of a region of a surface of the baseplate such that the recess has a first sidewall having a first thickness above a recess base and a second sidewall having a second thickness above the recess base. A substrate, e.g., a direct bonded copper (DBC) substrate, may be attached to the baseplate at a recess base using, e.g., a solder layer between the recess base and a surface of the substrate.

公开(公告)号：US20240355638A1

公开(公告)日：2024-10-24

申请号：US18760515

申请日：2024-07-01

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yong LIU ,  Yusheng LIN ,  Liangbiao CHEN

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/28 ,  H01L23/495 ,  H01L23/498

CPC classification number: H01L21/4821 ,  H01L21/56 ,  H01L23/28 ,  H01L23/49534 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49861

Abstract: Methods of forming semiconductor packages include providing a first insulator layer coupled with a first metallic layer. A recess is formed in the first metallic layer and a semiconductor die is mechanically coupled therein. The die is mechanically coupled with a second metallic layer and the second metallic layer is coupled with a second insulator layer. The die and layers are at least partially encapsulated to form the semiconductor package. The first and/or second metallic layers may be insulator-metal substrates, metal-insulator-metal (MIM) substrates, or may be formed of lead frames. In implementations the package does not include a spacer between the die and the first metallic layer and does not include a spacer between the die and the second metallic layer. In implementations the first insulator layer and the second insulator layer are exposed through the encapsulant or are mechanically coupled with metallic layers exposed through the encapsulant.

公开(公告)号：US12125884B2

公开(公告)日：2024-10-22

申请号：US18301146

申请日：2023-04-14

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Kevin Kyuheon Cho ,  Bongyong Lee ,  Kyeongseok Park ,  Doojin Choi ,  Thomas Neyer ,  Ki Min Kim

IPC: H01L29/16 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1608 ,  H01L29/1045 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/7802

Abstract: A SiC MOSFET device with alternating p-well widths, including an undulating channel, is described. The undulating channel provides current paths of multiple widths, which enables optimization of on-resistance, transconductance, threshold voltage, and channel length. The multi-width p-well region further defines corresponding multi-width Junction FETs (JFETs). The multi-width JFETs enable improved response to a short-circuit event. A high breakdown voltage is obtained by distributing a high electric field in a JFET of a first width into a JFET of a second width.

公开(公告)号：US20240332025A1

公开(公告)日：2024-10-03

申请号：US18742204

申请日：2024-06-13

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Francis J. CARNEY ,  Yusheng LIN ,  Michael J. SEDDON ,  Chee Hiong CHEW ,  Soon Wei WANG ,  Eiji KUROSE

IPC: H01L21/302 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/12 ,  H01L23/31

CPC classification number: H01L21/302 ,  H01L21/48 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/12 ,  H01L23/3185 ,  H01L24/04 ,  H01L24/26 ,  H01L2224/94

Abstract: Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; applying a permanent coating material into the plurality of notches; forming a first organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.

公开(公告)号：US12107173B2

公开(公告)日：2024-10-01

申请号：US18322249

申请日：2023-05-23

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Andrei Konstantinov

IPC: H01L29/872 ,  H01L21/04 ,  H01L21/761 ,  H01L29/04 ,  H01L29/06 ,  H01L29/16 ,  H01L29/36 ,  H01L29/66

CPC classification number: H01L29/872 ,  H01L21/046 ,  H01L21/0465 ,  H01L21/047 ,  H01L21/761 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/6606 ,  H01L29/045

Abstract: A SiC Schottky rectifier with surge current ruggedness is described. The Schottky rectifier includes one or more multi-layer bodies that provide multiple types of surge current protection.

公开(公告)号：US20240321924A1

公开(公告)日：2024-09-26

申请号：US18673521

申请日：2024-05-24

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jeffrey Peter GAMBINO ,  David T. PRICE ,  Marc Allen SULFRIDGE ,  Richard MAURITZSON ,  Michael Gerard KEYES ,  Ryan RETTMANN ,  Kevin MCSTAY

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14603 ,  H01L27/14623 ,  H01L27/1464

Abstract: An imaging device may include single-photon avalanche diodes (SPADs). To mitigate crosstalk, isolation structures may be formed around each SPAD. The isolation structures may include front side deep trench isolation structures that extend partially or fully through a semiconductor substrate for the SPADs. The isolation structures may include a metal filler such as tungsten that absorbs photons. The isolation structures may include a p-type doped semiconductor liner to mitigate dark current. The isolation structures may include a buffer layer such as silicon dioxide that is interposed between the metal filler and the p-type doped semiconductor liner. The isolation structures may have a tapered portion or may be formed in two steps such that the isolation structures have different portions with different properties. An additional filler such as polysilicon or borophosphosilicate glass may be included in some of the isolation structures in addition to the metal filler.

公开(公告)号：US20240314466A1

公开(公告)日：2024-09-19

申请号：US18182644

申请日：2023-03-13

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jhankar MALAKAR ,  Arindam RAYCHAUDHURI

IPC: H04N25/766 ,  H04N25/76 ,  H04N25/767

CPC classification number: H04N25/766 ,  H04N25/767 ,  H04N25/7795 ,  H04L7/0087

Abstract: Imaging circuitry may include half-driver sub-circuits configured to support Mobile Industry Processor Interface (MIPI) D-PHY mode and C-PHY mode. Groups of two half-driver sub-circuits can be coupled together in the D-PHY mode, whereas groups of three half-driver sub-circuits can be coupled together in the C-PHY mode. Each half-driver sub-circuit can include one or more pull-up paths and one or more pull-down paths. Each half-driver sub-circuit can include multiple slices, a first portion of which can be operated to pull in a first direction and a second portion of which can be operated to pull in a second direction opposing the first direction to achieve the desired amount of equalization. The half-driver sub-circuits can be employed as the final driver stage of a shared data path architecture supporting both D-PHY and C-PHY modes. The shared data path can include serializers, pre-driver logic, and/or equalization enable blocks.

公开(公告)号：US20240313719A1

公开(公告)日：2024-09-19

申请号：US18185441

申请日：2023-03-17

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Cornel D. STANESCU ,  Adrian Constantin VESELU

IPC: H03F3/393 ,  G01R19/00 ,  H03F3/45

CPC classification number: H03F3/393 ,  G01R19/0023 ,  H03F3/45475 ,  H03F2203/45248

Abstract: A high-voltage chopper-stabilized amplifier can include two paths to compensate for non-ideal electrical parameters. A first path, leading to a primary input of the amplifier, may include a first mux interface circuit to limit voltages at the primary input of the amplifier. A second path, leading to an auxiliary input of the amplifier, may include a chopper amplifier circuit. Despite the first mux interface circuit, a slew condition on the first path may excite a current in the second path that can negatively affect the signal source. Accordingly, the disclosed amplifier further includes a second mux interface circuit that can decouple the second path while a slew condition. The second mux interface circuit is driven by a window floating comparator, which is supplied according to the voltages on primary input. A settling enhancer circuit keeps, during slew condition, certain nodes on the second path at a reference voltage.

公开(公告)号：US20240313643A1

公开(公告)日：2024-09-19

申请号：US18669320

申请日：2024-05-20

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Armando Gabriel MESA ,  Ajay HARI

IPC: H02M1/42 ,  H02M1/32 ,  H02M1/44

CPC classification number: H02M1/4225 ,  H02M1/32 ,  H02M1/44

Abstract: During a light load (or no-load) operation of a totem pole power factor correction circuit (i.e., PFC), a pulse width modulation (PWM) controller can operate in a skip mode. Further, the PWM controller may disable portions of the PFC to reduce standby power consumption. In this mode, and in this disabled configuration, the output of the PFC may be peak charged over time to a voltage that could be damaging or destructive. This peak charging results from the PFC circuit's inability to fully charge/discharge EMI capacitors between half cycles of the input line voltage. The present disclosure provides circuits and methods to fully charge/discharge the EMI capacitors to prevent peak charging the output.