公开(公告)号：US07183639B2

公开(公告)日：2007-02-27

申请号：US10916917

申请日：2004-08-12

申请人： Ichiro Mihara ,  Takeshi Wakabayashi ,  Toshihiro Kido ,  Hiroyasu Jobetto ,  Yutaka Yoshino ,  Nobuyuki Kageyama ,  Daita Kohno ,  Jun Yoshizawa

发明人： Ichiro Mihara ,  Takeshi Wakabayashi ,  Toshihiro Kido ,  Hiroyasu Jobetto ,  Yutaka Yoshino ,  Nobuyuki Kageyama ,  Daita Kohno ,  Jun Yoshizawa

IPC分类号： H01L23/48

CPC分类号： H01L23/3128 ,  H01L21/56 ,  H01L23/16 ,  H01L23/3114 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

摘要： A semiconductor device includes at least one semiconductor structure which has a plurality of external connection electrodes formed on a semiconductor substrate. An insulating sheet member is arranged on the side of the semiconductor structure. Upper interconnections have connection pad portions that are arranged on the insulating sheet member in correspondence with the upper interconnections and connected to the external connection electrodes of the semiconductor structure.

摘要翻译： 半导体器件包括至少一个半导体结构，其具有形成在半导体衬底上的多个外部连接电极。 在半导体结构的一侧设置有绝缘片部件。 上部互连具有连接焊盘部分，其布置在与上部互连件对应并且连接到半导体结构的外部连接电极的绝缘片部件上。

公开(公告)号：US20060273463A1

公开(公告)日：2006-12-07

申请号：US11443858

申请日：2006-05-31

申请人： Takeshi Wakabayashi ,  Ichiro Mihara

发明人： Takeshi Wakabayashi ,  Ichiro Mihara

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/3114 ,  H01L23/5286 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05569 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： A semiconductor device includes a semiconductor substrate having an integrated circuit, a first insulating film formed on the semiconductor substrate, at least one power source internal wiring line formed on the first insulating film, and a second insulating film formed on the first insulating film and on the internal wiring line and having a plurality of openings exposing parts of the internal wiring line. At least one wiring line is formed on an upper side of the second insulating film to correspond to the internal wiring line and electrically connected to the internal wiring line via the plurality of openings of the second insulating film. The wiring line has at least one external electrode pad portion whose number is smaller than the number of openings in the second insulating film.

摘要翻译： 半导体器件包括具有集成电路的半导体衬底，形成在半导体衬底上的第一绝缘膜，形成在第一绝缘膜上的至少一个电源内部布线和形成在第一绝缘膜上的第二绝缘膜， 内部布线并且具有暴露内部布线的部分的多个开口。 至少一条布线形成在第二绝缘膜的上侧，以对应于内部布线，并且经由第二绝缘膜的多个开口与内部布线相电连接。 布线具有数量小于第二绝缘膜中的开口数量的至少一个外部电极焊盘部分。

公开(公告)号：US20060202353A1

公开(公告)日：2006-09-14

申请号：US11429368

申请日：2006-05-05

申请人： Takeshi Wakabayashi ,  Ichiro Mihara

发明人： Takeshi Wakabayashi ,  Ichiro Mihara

IPC分类号： H01L23/48

CPC分类号： H01L21/6835 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/16225 ,  H01L2224/24195 ,  H01L2224/24226 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/83 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/07811 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

摘要： A plurality of semiconductor chips are bonded to an adhesive layer formed on a base plate. Then, first to third insulating films, first and second underlying metal layers, first and second re-wirings, and a solder ball are collectively formed for the plural semiconductor chips. In this case, the first and second underlying metal layers are formed by a sputtering method, and the first and second re-wirings are formed by an electroplating method. Then, a laminate structure consisting of the three insulating films, the adhesive layer, and the base plate is cut in a region positioned between the adjacent semiconductor chips.

摘要翻译： 多个半导体芯片被接合到形成在基板上的粘合剂层。 然后，对于多个半导体芯片，共同形成第一至第三绝缘膜，第一和第二下面的金属层，第一和第二重新布线以及焊球。 在这种情况下，通过溅射法形成第一和第二基底金属层，并且通过电镀方法形成第一和第二重新布线。 然后，在位于相邻的半导体芯片之间的区域中切割由三个绝缘膜，粘合剂层和基板组成的层叠结构。

公开(公告)号：US20050098891A1

公开(公告)日：2005-05-12

申请号：US10472803

申请日：2003-02-03

申请人： Takeshi Wakabayashi ,  Ichiro Mihara

发明人： Takeshi Wakabayashi ,  Ichiro Mihara

IPC分类号： H01L21/58 ,  H01L21/60 ,  H01L21/68 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10 ,  H01L23/485

CPC分类号： H01L21/6835 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/16225 ,  H01L2224/24195 ,  H01L2224/24226 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/83 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/07811 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

摘要： A plurality of semiconductor chips (23) are bonded to an adhesive layer (22) formed on a base plate (21). Then, first to third insulating films (31, 35, 39), first and second underlying metal layers (33, 37), first and second re-wirings (34, 38), and a solder ball (41) are collectively formed for the plural semiconductor chips (23). In this case, the first and second underlying metal layers (33, 37) are formed by a sputtering method, and the first and second re-wirings (34, 38) are formed by an electroplating method. Then, a laminate structure consisting of the three insulating films (39, 35, 31), the adhesive layer (22), and the base plate (21) is cut in a region positioned between the adjacent semiconductor chips (23).

摘要翻译： 多个半导体芯片（23）被接合到形成在基板（21）上的粘合剂层（22）上。 然后，共同形成第一至第三绝缘膜（31,35,39），第一和第二下面的金属层（33,37），第一和第二重新布线（34,38）以及焊球（41） 多个半导体芯片（23）。 在这种情况下，通过溅射法形成第一和第二下面的金属层（33,37），并且通过电镀方法形成第一和第二重新布线（34,38）。 然后，在位于相邻的半导体芯片（23）之间的区域中切割由三个绝缘膜（39,35,31），粘合剂层（22）和基板（21）组成的层叠结构。

公开(公告)号：US20050084989A1

公开(公告)日：2005-04-21

申请号：US10964019

申请日：2004-10-12

申请人： Takeshi Wakabayashi ,  Ichiro Mihara

发明人： Takeshi Wakabayashi ,  Ichiro Mihara

IPC分类号： H01L21/66 ,  G01R31/28 ,  H01L21/56 ,  H01L23/12 ,  H01L23/31 ,  H01L23/485

CPC分类号： H01L24/10 ,  G01R31/2863 ,  G01R31/2886 ,  H01L23/3114 ,  H01L24/13 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00014

摘要： After columnar electrodes and a sealing film are formed above a semiconductor substrate in a wafer state, probe pins are brought into contact with the upper surfaces of the columnar electrodes, and burn-in is executed. Next, solder balls are formed on the columnar electrodes, and the semiconductor substrate in a wafer state is diced. As a result, any unwanted deformation of the solder balls by contact of the probe pins can be prevented. In addition, even when the heights of the solder balls vary, burn-in can be performed.

摘要翻译： 在晶片状态的半导体基板的上方形成柱状电极和密封膜之后，使探针与柱状电极的上表面接触，进行老化。 接下来，在柱状电极上形成焊球，切割晶片状态的半导体基板。 结果，可以防止焊球通过探针的接触而引起的任何不希望的变形。 此外，即使当焊球的高度变化时，也可以进行老化。

公开(公告)号：US06870256B2

公开(公告)日：2005-03-22

申请号：US10254222

申请日：2002-09-25

申请人： Yutaka Aoki ,  Ichiro Mihara ,  Takeshi Wakabayashi ,  Katsumi Watanabe

发明人： Yutaka Aoki ,  Ichiro Mihara ,  Takeshi Wakabayashi ,  Katsumi Watanabe

IPC分类号： H01L21/3205 ,  H01L20060101 ,  H01L21/60 ,  H01L21/822 ,  H01L23/50 ,  H01L23/52 ,  H01L23/522 ,  H01L27/00 ,  H01L27/04 ,  H01L29/40 ,  H01L31/00

CPC分类号： H01L23/3114 ,  H01L23/5223 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/525 ,  H01L2924/0002 ,  H01L2924/1423 ,  H01L2924/19041 ,  H01L2924/00

摘要： In a semiconductor device, re-wiring is provided on a circuit element formation region of a semiconductor substrate. A columnar electrode for connection with a circuit board is provided on the rewiring. A first insulating film is provided over the semiconductor substrate excluding a connection pad, and a ground potential layer connected to a ground potential is provided on an upper surface of the first insulating film. A re-wiring is provided over the ground potential layer with a second insulating film interposed. The ground potential layer serves as a barrier layer for preventing crosstalk between the re-wiring and circuit element formation region. A thin-film circuit element is provided on the second insulating film, and a second ground potential layer is provided as a second barrier layer over the thin-film circuit element with an insulating film interposed. Re-wiring is provided over the second ground potential layer.

摘要翻译： 在半导体器件中，在半导体衬底的电路元件形成区域上设置再布线。 在重新布线时提供用于与电路板连接的柱状电极。 第一绝缘膜设置在除了连接焊盘之外的半导体衬底上，并且在第一绝缘膜的上表面上设置连接到接地电位的接地电位层。 在地电位层上提供再布线，其中插入有第二绝缘膜。 地电位层用作防止重新布线和电路元件形成区域之间的串扰的阻挡层。 薄膜电路元件设置在第二绝缘膜上，第二接地电位层设置在薄膜电路元件上，作为第二阻挡层，绝缘膜被插入。 在第二接地电位层上提供重新布线。

公开(公告)号：US20050051886A1

公开(公告)日：2005-03-10

申请号：US10916917

申请日：2004-08-12

申请人： Ichiro Mihara ,  Takeshi Wakabayashi ,  Toshihiro Kido ,  Hiroyasu Jobetto ,  Yutaka Yoshino ,  Nobuyuki Kageyama ,  Daita Kohno ,  Jun Yoshizawa

发明人： Ichiro Mihara ,  Takeshi Wakabayashi ,  Toshihiro Kido ,  Hiroyasu Jobetto ,  Yutaka Yoshino ,  Nobuyuki Kageyama ,  Daita Kohno ,  Jun Yoshizawa

IPC分类号： H01L21/56 ,  H01L23/16 ,  H01L23/31 ,  H01L23/48

CPC分类号： H01L23/3128 ,  H01L21/56 ,  H01L23/16 ,  H01L23/3114 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

摘要： A semiconductor device includes at least one semiconductor structure which has a plurality of external connection electrodes formed on a semiconductor substrate. An insulating sheet member is arranged on the side of the semiconductor structure. Upper interconnections have connection pad portions that are arranged on the insulating sheet member in correspondence with the upper interconnections and connected to the external connection electrodes of the semiconductor structure.

摘要翻译： 半导体器件包括至少一个半导体结构，其具有形成在半导体衬底上的多个外部连接电极。 在半导体结构的一侧设置有绝缘片部件。 上部互连具有连接焊盘部分，其布置在与上部互连件对应并且连接到半导体结构的外部连接电极的绝缘片部件上。

公开(公告)号：US6140155A

公开(公告)日：2000-10-31

申请号：US459019

申请日：1999-12-10

申请人： Ichiro Mihara ,  Shoichi Kotani ,  Takeshi Wakabayashi ,  Masami Hiramoto

发明人： Ichiro Mihara ,  Shoichi Kotani ,  Takeshi Wakabayashi ,  Masami Hiramoto

IPC分类号： H01L21/60 ,  H01L21/68 ,  H01L23/485 ,  H01L24/50

CPC分类号： H01L21/6835 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/68313 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01052 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14

摘要： A plating tray includes a recessed region in a central portion of an insulating substrate for arranging therein a silicon semiconductor substrate and a metal film arranged to surround the recessed region. The semiconductor substrate is housed in the recessed region. Under this condition, a dry photoresist film containing Na, K, Ca and Cu in amounts smaller than predetermined amounts is formed to cover a metal underlying film. Then, a projecting electrode is formed by electroplating within open portions formed in the resist film. In forming the projecting electrode, the open portion is also formed in that region of the resist film which corresponds to the metal film of the plating plate so as to form a dummy projection electrode simultaneously.

摘要翻译： 电镀托盘包括在绝缘基板的中心部分中的凹陷区域，用于在其中布置硅半导体衬底和布置成围绕凹陷区域的金属膜。 半导体衬底容纳在凹陷区域中。 在这种条件下，形成含有小于预定量的Na，K，Ca和Cu的干的光致抗蚀剂膜以覆盖金属底层膜。 然后，通过在形成在抗蚀剂膜上的开口部内进行电镀而形成突出电极。 在形成突出电极时，开口部也形成在对应于电镀板的金属膜的抗蚀剂膜的区域中，以同时形成虚设的投影电极。

公开(公告)号：US08154133B2

公开(公告)日：2012-04-10

申请号：US12412576

申请日：2009-03-27

申请人： Taisuke Koroku ,  Takeshi Wakabayashi ,  Osamu Okada ,  Osamu Kuwabara ,  Junji Shiota ,  Nobumitsu Fujii

发明人： Taisuke Koroku ,  Takeshi Wakabayashi ,  Osamu Okada ,  Osamu Kuwabara ,  Junji Shiota ,  Nobumitsu Fujii

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/3114 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3135 ,  H01L24/11 ,  H01L24/12 ,  H01L24/27 ,  H01L2221/6834 ,  H01L2221/68372 ,  H01L2221/68377 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/11 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/94 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/10157 ,  H01L2924/10158 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3512 ,  H01L2924/00

摘要： A low dielectric constant film/wiring line stack structure made up of a stack of low dielectric constant films and wiring lines is provided in a region on the upper surface of the semiconductor substrate except for the peripheral part of this surface. The peripheral side surface of the low dielectric constant film/wiring line stack structure is covered with a sealing film. This provides a structure in which the low dielectric constant films do not easily come off. In this case, a lower protective film is provided on the lower surface of a silicon substrate to protect this lower surface against cracks.

摘要翻译： 在半导体基板的上表面的除了该表面的周边部分之外的区域中设置由低介电常数膜和布线组成的低介电常数膜/布线层叠结构。 低介电常数薄膜/布线层叠结构的周边侧表面被密封膜覆盖。 这提供了低介电常数膜不容易脱落的结构。 在这种情况下，在硅基板的下表面上设置下保护膜，以保护该下表面免受裂纹。

公开(公告)号：US20090243097A1

公开(公告)日：2009-10-01

申请号：US12412576

申请日：2009-03-27

申请人： Taisuke KOROKU ,  Takeshi Wakabayashi ,  Osamu Okada ,  Osamu Kuwabara ,  Junji Shiota ,  Nobumitsu Fujii

发明人： Taisuke KOROKU ,  Takeshi Wakabayashi ,  Osamu Okada ,  Osamu Kuwabara ,  Junji Shiota ,  Nobumitsu Fujii

IPC分类号： H01L23/488 ,  H01L21/762

CPC分类号： H01L23/3114 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3135 ,  H01L24/11 ,  H01L24/12 ,  H01L24/27 ,  H01L2221/6834 ,  H01L2221/68372 ,  H01L2221/68377 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/11 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/94 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/10157 ,  H01L2924/10158 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3512 ,  H01L2924/00

摘要： A low dielectric constant film/wiring line stack structure made up of a stack of low dielectric constant films and wiring lines is provided in a region on the upper surface of the semiconductor substrate except for the peripheral part of this surface. The peripheral side surface of the low dielectric constant film/wiring line stack structure is covered with a sealing film. This provides a structure in which the low dielectric constant films do not easily come off. In this case, a lower protective film is provided on the lower surface of a silicon substrate to protect this lower surface against cracks.

摘要翻译： 在半导体基板的上表面的除了该表面的周边部分之外的区域中设置由低介电常数膜和布线组成的低介电常数膜/布线层叠结构。 低介电常数薄膜/布线层叠结构的周边侧表面被密封膜覆盖。 这提供了低介电常数膜不容易脱落的结构。 在这种情况下，在硅基板的下表面上设置下保护膜，以保护该下表面免受裂纹。