中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

55 records (took 0.02 seconds)

    Active probe card for electrical wafer sort of integrated circuits
    44.
    发明授权
    Active probe card for electrical wafer sort of integrated circuits 有权
    用于电子晶圆的主动探针卡集成电路

    公开(公告)号：US09176185B2

    公开(公告)日：2015-11-03

    申请号：US13558210

    申请日：2012-07-25

    Applicant: Roberto Canegallo ,  Mauro Scandiuzzo ,  Roberto Cardu ,  Eleonora Franchi Scarselli ,  Alberto Pagani

    Inventor： Roberto Canegallo ,  Mauro Scandiuzzo ,  Roberto Cardu ,  Eleonora Franchi Scarselli ,  Alberto Pagani

    IPC: G01R31/02 ,  G01R31/20 ,  G01R31/28 ,  G01R31/302

    CPC classification number: G01R31/2889 ,  G01R31/3025

    Abstract: A testing apparatus includes a tester and a probe card system that includes a probe card connected to the tester, and an active interposer connected to the probe card and wirelessly coupled with a device to be tested. The active interposer includes pads positioned on its free surface facing the device. The pads are positioned with respect to pads of the device so that each pad of the active interposer faces a pad of the device and is separated therefrom by a dielectric. Each pair of facing pads forms an elementary wireless coupling element which allows a wireless transmission between the active interposer and the device. The active interposer also includes an amplifier circuit configured to amplify wireless signals from the device before forwarding them to the tester. The probe card system includes a transmission element able to transmit a power voltage from the tester to the device.

    Abstract translation: 测试装置包括测试器和探针卡系统，其包括连接到测试器的探针卡，以及连接到探针卡并与要测试的设备无线耦合的有源插入器。 有源插入器包括位于其面向设备的自由表面上的焊盘。 焊盘相对于器件的焊盘定位，使得有源插入器的每个焊盘面向器件的焊盘并且通过电介质与其分离。 每对相对的焊盘形成基本无线耦合元件，其允许在有源插入器和设备之间进行无线传输。 有源插入器还包括放大器电路，其被配置为在将它们转发到测试器之前放大来自器件的无线信号。 探针卡系统包括能够从测试仪向设备传输电力电压的传输元件。

    Sensing structure of alignment of a probe for testing integrated circuits
    45.
    发明授权
    Sensing structure of alignment of a probe for testing integrated circuits 有权
    用于测试集成电路的探头对准的感应结构

    公开(公告)号：US09134367B2

    公开(公告)日：2015-09-15

    申请号：US13155623

    申请日：2011-06-08

    Applicant: Alberto Pagani

    Inventor： Alberto Pagani

    IPC: G01R31/00 ,  G01R31/28 ,  C12Q1/00 ,  G01R1/067 ,  H01L21/66

    CPC classification number: G01R31/2891 ,  C12Q1/00 ,  C12Q2304/00 ,  C12Q2326/00 ,  G01R1/06794 ,  G01R31/2884 ,  H01L21/00 ,  H01L22/34 ,  H01L2221/00 ,  H01L2924/00

    Abstract: A sensing structure for use in testing integrated circuits on a substrate. The sensing structure includes at least two sensing regions connectable to a probe and at least one first sensing element. Each of the at least one first sensing elements is directly connected to two sensing regions such that for each sensing region a different value of an electrical parameter is measurable between the sensing region and a first reference potential so as to reliably determine a drift direction of a probe.

    Abstract translation: 用于在基板上测试集成电路的感测结构。 感测结构包括可连接到探针和至少一个第一感测元件的至少两个感测区域。 所述至少一个第一感测元件中的每一个直接连接到两个感测区域，使得对于每个感测区域，在所述感测区域和第一参考电位之间可测量电参数的不同值，以便可靠地确定所述感测区域的漂移方向 探测。

    System and method for electrical testing of through silicon vias (TSVs)
    46.
    发明授权
    System and method for electrical testing of through silicon vias (TSVs) 有权
    通过硅通孔（TSV）的电气测试系统和方法

    公开(公告)号：US09111895B2

    公开(公告)日：2015-08-18

    申请号：US13579562

    申请日：2011-02-16

    Applicant: Alberto Pagani

    Inventor： Alberto Pagani

    IPC: G01R31/02 ,  H01L21/66 ,  H01L21/768

    CPC classification number: G01R31/275 ,  G01R31/2853 ,  H01L21/76898 ,  H01L22/34 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An embodiment of a testing system for carrying out electrical testing of at least one first through via extending, at least in part, through a substrate of a first body of semiconductor material. The testing system has a first electrical test circuit integrated in the first body and electrically coupled to the first through via and to electrical-connection elements carried by the first body for electrical connection towards the outside; the first electrical test circuit enables detection of at least one electrical parameter of the first through via through the electrical-connection elements.

    Abstract translation: 用于进行至少一个第一通孔的电测试的测试系统的实施例，所述至少一个第一通孔至少部分地延伸穿过第一半导体材料体的衬底。 测试系统具有集成在第一主体中并与第一通孔电耦合的第一电测试电路和由第一主体携带的电连接元件，用于电连接到外部; 第一电测试电路使得能够通过电连接元件检测第一通孔的至少一个电参数。

    RETINAL PROSTHESIS
    47.
    发明申请
    RETINAL PROSTHESIS 有权

    公开(公告)号：US20130282119A1

    公开(公告)日：2013-10-24

    申请号：US13977121

    申请日：2011-12-30

    Applicant: Alberto Pagani

    Inventor： Alberto Pagani

    IPC: A61F2/14

    CPC classification number: A61F2/14 ,  A61F2/148 ,  A61F9/08 ,  A61F2250/0002 ,  A61N1/0543 ,  A61N1/36 ,  A61N1/36046

    Abstract: A retinal prosthesis including an electronic stimulation unit housed inside an eye and including: a plurality of electrodes that contact a portion of a retina of the eye; an electronic control circuit, which is electrically connected to the electrodes and supplies to the electrodes electrical stimulation signals designed to stimulate the portion of retina; and a local antenna connected to the electronic control circuit. The retinal prosthesis further includes an electromagnetic expansion housed inside the eye and formed by a first expansion antenna and a second expansion antenna electrically connected together, the first expansion antenna being magnetically or electromagnetically coupled to an external antenna, the second expansion antenna being magnetically or electromagnetically couple to the local antenna, the electromagnetic expansion moreover receiving an electromagnetic supply signal transmitted by the external antenna and generating a corresponding replica signal.

    Abstract translation: 一种视网膜假体，包括容纳在眼睛内的电子刺激单元，包括：多个电极，其接触眼睛的视网膜的一部分; 电子控制电路，电连接到电极并向电极提供设计成刺激视网膜部分的电刺激信号; 以及连接到电子控制电路的本地天线。 视网膜假体还包括容纳在眼睛内部并由第一扩展天线和电连接在一起的第二扩展天线形成的电磁膨胀，第一扩展天线被磁或电磁耦合到外部天线，第二扩展天线是磁性或电磁学的 耦合到本地天线，电磁膨胀还接收由外部天线发送的电磁供给信号并产生相应的复制信号。

    Circuit architecture for the parallel supplying during electric or electromagnetic testing of a plurality of electronic devices integrated on a semiconductor wafer
    48.
    发明授权
    Circuit architecture for the parallel supplying during electric or electromagnetic testing of a plurality of electronic devices integrated on a semiconductor wafer 有权
    用于在集成在半导体晶片上的多个电子设备的电或电磁测试期间并联供电的电路架构

    公开(公告)号：US08378346B2

    公开(公告)日：2013-02-19

    申请号：US13022419

    申请日：2011-02-07

    Applicant: Alberto Pagani

    Inventor： Alberto Pagani

    IPC: H01L23/58

    CPC classification number: H01L22/32 ,  G01R31/2884 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A circuit architecture provides for the parallel supplying of power during electric or electromagnetic testing of electronic devices integrated on a same semiconductor wafer and bounded by scribe lines. The circuit architecture comprises a conductive grid interconnecting the electronic devices and having a portion external to the devices and a portion internal to the devices. The external portion extends along the scribe lines; and the internal portion extends within at least a part of the devices. The circuit architecture includes interconnection pads between the external portion and the internal portion of the conductive grid and provided on at least a part of the devices, the interconnection pads forming, along with the internal and external portions, power supply lines which are common to different electronic devices of the group.

    Abstract translation: 电路架构提供了在同一半导体晶片上并且由划线界定的电子设备的电或电磁测试期间并联供电。 电路架构包括将电子设备互连并且具有设备外部的部分和设备内部的部分的导电栅格。 外部部分沿划线延伸; 并且内部部分在装置的至少一部分内延伸。 电路结构包括在导电栅格的外部部分和内部部分之间并且设置在至少一部分器件上的互连焊盘，互连焊盘与内部和外部部分形成不同的电源线 电子设备组。

    Testing integrated circuits using few test probes
    49.
    发明授权
    Testing integrated circuits using few test probes 有权
    使用少量测试探针测试集成电路

    公开(公告)号：US08362796B2

    公开(公告)日：2013-01-29

    申请号：US12398148

    申请日：2009-03-04

    Applicant: Alberto Pagani

    Inventor： Alberto Pagani

    IPC: G01R31/02

    CPC classification number: G01R31/2841 ,  G01R31/2851 ,  G01R31/3172 ,  G01R31/31905 ,  G01R31/31926 ,  H01L22/30 ,  H01L2224/16 ,  H01L2924/1461 ,  H01L2924/00

    Abstract: A method of testing integrated circuits, including: establishing at least a first physical communication channel between a test equipment and an integrated circuit under test by having at least a first probe of the test equipment contacting a corresponding physical contact terminal of the integrated circuit under test; having the test equipment and the integrated circuit under test exchange, over said first physical communication channel, at least two signals selected from the group including at least two test stimuli and at least two test response signals, wherein said at least two signals are exchanged by means of at least one modulated carrier wave modulated by the at least two signals.

    Abstract translation: 一种测试集成电路的方法，包括：通过使测试设备的至少第一探针与被测集成电路的对应的物理接触端子相接触来在测试设备和被测集成电路之间建立至少第一物理通信通道 ; 使所述测试设备和被测集成电路交换，通过所述第一物理通信信道，从包括至少两个测试刺激和至少两个测试响应信号的组中选出的至少两个信号，其中所述至少两个信号由 由至少两个信号调制的至少一个调制载波的装置。

Patent Agency Ranking