公开(公告)号：US06515342B1

公开(公告)日：2003-02-04

申请号：US09557680

申请日：2000-04-25

申请人： Subhash Gupta ,  Bhanwar Singh ,  Carmen Morales

发明人： Subhash Gupta ,  Bhanwar Singh ,  Carmen Morales

IPC分类号： H01L2900

CPC分类号： G03F7/16 ,  H01L21/02134 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/0274 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/3124

摘要： A system and method for forming a plurality of structures in a low dielectric constant layer is disclosed. The low dielectric constant layer is disposed on a semiconductor. The method and system include exposing the low dielectric constant layer to an agent that improves adhesion of a photoresist, providing a layer of the photoresist on the low dielectric constant layer, patterning the photoresist, and etching the low dielectric constant layer to form the plurality of structures.

摘要翻译： 公开了一种用于在低介电常数层中形成多个结构的系统和方法。 低介电常数层设置在半导体上。 所述方法和系统包括将低介电常数层暴露于改善光致抗蚀剂的粘附性的试剂，在低介电常数层上提供光致抗蚀剂层，图案化光致抗蚀剂，以及蚀刻低介电常数层以形成多个 结构。

公开(公告)号：US06417088B1

公开(公告)日：2002-07-09

申请号：US09624019

申请日：2000-07-24

申请人： Kwok Keung Paul Ho ,  Yi Xu ,  Simon Chooi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Leonard Sudijono ,  Subhash Gupta ,  Sudipto Ranendra Roy

发明人： Kwok Keung Paul Ho ,  Yi Xu ,  Simon Chooi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Leonard Sudijono ,  Subhash Gupta ,  Sudipto Ranendra Roy

IPC分类号： H01L2144

CPC分类号： H01L24/48 ,  H01L21/288 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/45 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48644 ,  H01L2224/48699 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/48744

摘要： A method of forming a conductive cap layer over a metal bonding pad comprises the following steps. A semiconductor structure is provided having an exposed, recessed metal bonding pad within a layer opening. The layer has an upper surface. The exposed metal bonding pad is treated with a solution containing soluble metal ions to form a conductive cap over the metal bonding pad. The conductive cap layer is comprised of the solution metal and has a predetermined thickness. An external bonding element may then be bonded to the conductive cap, forming an electrical connection with the metal bonding pad.

摘要翻译： 在金属焊盘上形成导电盖层的方法包括以下步骤。 提供了一种半导体结构，其在层开口内具有暴露的凹陷的金属接合焊盘。 该层具有上表面。 暴露的金属焊盘用含有可溶性金属离子的溶液处理，以在金属焊盘上形成导电盖。 导电盖层由溶液金属构成并具有预定的厚度。 然后可以将外部接合元件接合到导电盖，与金属接合焊盘形成电连接。

公开(公告)号：US06394114B1

公开(公告)日：2002-05-28

申请号：US09442312

申请日：1999-11-22

申请人： Subhash Gupta ,  Simon Chooi ,  Paul Ho ,  Mei Sheng Zhou

发明人： Subhash Gupta ,  Simon Chooi ,  Paul Ho ,  Mei Sheng Zhou

IPC分类号： C23G114

CPC分类号： H01L21/32134 ,  C23F1/34 ,  H01L21/7684 ,  Y10S134/902

摘要： An inexpensive and safe copper removal method in the fabrication of integrated circuits is described. Copper is stripped or removed by a chemical mixture comprising an ammonium salt, an amine, and water. The rate of copper stripping can be controlled by varying the concentration of the ammonium salt component and the amount of water in the mixture. Also a novel chemical mixture for stripping copper and removing copper contamination is provided. The novel chemical mixture for removing or stripping copper comprises an ammonium salt, an amine, and water. For example, the novel chemical mixture may comprise ammonium fluoride, water, and ethylenediamine in a ratio of 1:1:1.

摘要翻译： 描述了在制造集成电路中的便宜且安全的铜去除方法。 通过包含铵盐，胺和水的化学混合物将铜剥离或除去。 可以通过改变铵盐组分的浓度和混合物中的水量来控制铜汽提速率。 还提供了一种用于剥离铜并除去铜污染物的新型化学混合物。 用于除去或剥离铜的新型化学混合物包括铵盐，胺和水。 例如，新型化学混合物可以包含比例为1:1:1的氟化铵，水和乙二胺。

公开(公告)号：US06391783B1

公开(公告)日：2002-05-21

申请号：US09615811

申请日：2000-07-13

申请人： John Sudijono ,  Yakub Aliyu ,  Mei Sheng Zhou ,  Simon Chooi ,  Subhash Gupta ,  Sudipto Roy ,  Paul Ho ,  Yi Xu

发明人： John Sudijono ,  Yakub Aliyu ,  Mei Sheng Zhou ,  Simon Chooi ,  Subhash Gupta ,  Sudipto Roy ,  Paul Ho ,  Yi Xu

IPC分类号： H01L2131

CPC分类号： H01L21/76844 ,  H01L21/288 ,  H01L21/76867

摘要： A method of forming a metal plug, comprising the following steps. An etched dielectric layer, over a conductive layer, over a semiconductor structure are provided. The etched dielectric layer having a via hole and an exposed periphery. The etched dielectric layer is treated with at least one alkaline earth element source to form an in-situ metal barrier layer within the dielectric layer exposed periphery. A metal plug is formed within the via hole wherein the in-situ metal barrier layer prevents diffusion of the metal from the metal plug into the dielectric oxide layer.

摘要翻译： 一种形成金属塞的方法，包括以下步骤。 提供了在半导体结构之上的导电层上的蚀刻介电层。 蚀刻的介电层具有通孔和暴露的周边。 蚀刻的电介质层用至少一个碱土元素源处理，以在电介质层外露的外围形成原位金属阻挡层。 在通孔内形成金属塞，其中原位金属阻挡层防止金属从金属塞扩散到电介质氧化物层中。

公开(公告)号：US06378759B1

公开(公告)日：2002-04-30

申请号：US09618261

申请日：2000-07-18

申请人： Kwok Keung Paul Ho ,  Simon Chooi ,  Yi Xu ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Leonard Sudijono ,  Subhash Gupta ,  Sudipto Ranendra Roy

发明人： Kwok Keung Paul Ho ,  Simon Chooi ,  Yi Xu ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Leonard Sudijono ,  Subhash Gupta ,  Sudipto Ranendra Roy

IPC分类号： B23K3102

CPC分类号： H01L24/85 ,  B23K20/007 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/04953 ,  H01L2224/78 ,  H01L2924/00

摘要： A method of bonding a bonding element to a metal bonding pad comprises the following steps. A semiconductor structure having an exposed, recessed metal bonding pad within a layer opening is provided. The layer has an upper surface. A conductive cap having a predetermined thickness is formed over the metal bonding pad. A bonding element is bonded to the conductive cap to form an electrical connection with the metal bonding pad.

摘要翻译： 将接合元件接合到金属接合焊盘的方法包括以下步骤。 提供了一种在层开口内具有暴露的凹陷金属接合焊盘的半导体结构。 该层具有上表面。 在金属焊盘上形成具有预定厚度的导电盖。 接合元件结合到导电盖以与金属接合焊盘形成电连接。

公开(公告)号：US06350689B1

公开(公告)日：2002-02-26

申请号：US09839962

申请日：2001-04-23

申请人： Paul Ho ,  Simon Chooi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Sudijono ,  Subhash Gupta ,  Sudipto Ranendra Roy ,  Yi Xu

发明人： Paul Ho ,  Simon Chooi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Sudijono ,  Subhash Gupta ,  Sudipto Ranendra Roy ,  Yi Xu

IPC分类号： H01L2144

CPC分类号： H01L21/02074 ,  H01L21/02046 ,  H01L21/0209 ,  H01L21/32136 ,  Y10S438/906

摘要： A method of removing copper contamination from a semiconductor wafer, comprising the following steps. A semiconductor wafer having copper contamination thereon is provided. An oxidizing radical containing downstream plasma is provided from a first source (alternatively halogen (F2, Cl2, or Br2) may be used as on oxidizing agent). A vaporized chelating agent is provided from a second source. The oxidizing radical containing downstream plasma and vaporized chelating agent are mixed to form an oxidizing radical containing downstream plasma/vaporized chelating agent mixture. The mixture is directed to the copper contamination so that the mixture reacts with the copper contamination to form a volatile product. The volatile product is removed from the proximity of the wafer.

摘要翻译： 一种从半导体晶片去除铜污染的方法，包括以下步骤。 提供其上具有铜污染的半导体晶片。 从第一来源提供含有下游等离子体的氧化基团（或者可以在氧化剂上使用卤素（F2，Cl2或Br2））。 从第二来源提供蒸发的螯合剂。 将含有下游等离子体和气化螯合剂的氧化基团混合以形成含有下游等离子体/汽化螯合剂混合物的氧化基团。 混合物被引导到铜污染物，使得混合物与铜污染物反应形成挥发性产物。 从晶片附近去除挥发性产物。

公开(公告)号：US06313018B1

公开(公告)日：2001-11-06

申请号：US09504449

申请日：2000-02-16

申请人： Fei Wang ,  David K. Foote ,  Myron R. Cagan ,  Subhash Gupta

发明人： Fei Wang ,  David K. Foote ,  Myron R. Cagan ,  Subhash Gupta

IPC分类号： H01L2120

CPC分类号： H01L21/0214 ,  H01L21/02126 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0276 ,  H01L21/3121 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A microelectronic device such as a Metal-Oxide-Semiconductor (MOS) transistor is formed on a semiconductor substrate. A tungsten damascene interconnect for the device is formed using an etch stop layer of silicon nitride, silicon oxynitride or silicon oxime having a high silicon content of approximately 40% to 50% by weight. The etch stop layer has high etch selectivity relative to overlying insulator materials such as silicon dioxide, tetraethylorthosilicate (TEOS) glass and borophosphosilicate glass (BPSG). The etch stop layer also has a high index of refraction and is anti-reflective, thereby improving critical dimension control during photolithographic imaging.

摘要翻译： 在半导体衬底上形成诸如金属氧化物半导体（MOS）晶体管的微电子器件。 用于器件的钨镶嵌互连使用具有大约40％至50％重量的硅含量的氮化硅，氮氧化硅或硅肟的蚀刻停止层形成。 蚀刻停止层相对于上覆绝缘体材料如二氧化硅，原硅酸四乙酯（TEOS）玻璃和硼磷硅酸盐玻璃（BPSG）具有高蚀刻选择性。 蚀刻停止层还具有高折射率并且是抗反射性的，从而改善光刻成像期间的临界尺寸控制。

公开(公告)号：US06284657B1

公开(公告)日：2001-09-04

申请号：US09512379

申请日：2000-02-25

申请人： Simon Chooi ,  Subhash Gupta ,  Mei-Sheng Zhou ,  Sangki Hong

发明人： Simon Chooi ,  Subhash Gupta ,  Mei-Sheng Zhou ,  Sangki Hong

IPC分类号： H01L2144

CPC分类号： H01L21/76832 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76831

摘要： A method for forming dual-damascene type conducting interconnects with non-metallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly suited for forming such interconnects in microelectronics fabrications of the sub 0.15 micron generation.

摘要翻译： 用于形成具有非金属屏障的双镶嵌型导电互连的方法，其保护所述互连免受氟周围的低k，氟化介电材料的氟扩散。 该方法的一个实施例特别适用于在0.15微米级的微电子制造中形成这种互连。

公开(公告)号：US06172421B2

公开(公告)日：2001-01-09

申请号：US09132282

申请日：1998-08-11

申请人： Paul Raymond Besser ,  Shekhar Pramanick ,  Takeshi Nogami ,  Subhash Gupta

发明人： Paul Raymond Besser ,  Shekhar Pramanick ,  Takeshi Nogami ,  Subhash Gupta

IPC分类号： H01L2348

CPC分类号： H01L21/76858 ,  H01L21/76849 ,  H01L21/76886

摘要： The present invention relates to the formation of a protective intermetallic layer 15 on the surface of damascene metal interconnects 12 during semiconductor fabrication. The intermetallic layer 15 prevents problems associated with formation of an oxide layer on the surface of the interconnect. The intermetallic layer is formed by depositing a metal on the surface of the interconnect that will both reduce any present metal oxide layer and form an intermetallic with the interconnect metal.

摘要翻译： 本发明涉及在半导体制造期间在镶嵌金属互连件12的表面上形成保护性金属间化合物层15。 金属间层15防止与互连表面上形成氧化物层有关的问题。 金属间化合物层通过在互连表面上沉积金属而形成，该金属将既减少任何存在的金属氧化物层并与互连金属形成金属间化合物。

公开(公告)号：US6051882A

公开(公告)日：2000-04-18

申请号：US905974

申请日：1997-08-05

申请人： Steven Avanzino ,  Subhash Gupta ,  Rich Klein ,  Scott D. Luning ,  Ming-Rin Lin

发明人： Steven Avanzino ,  Subhash Gupta ,  Rich Klein ,  Scott D. Luning ,  Ming-Rin Lin

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/52

CPC分类号： H01L23/5226 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76877 ,  H01L21/76885 ,  H01L2924/0002

摘要： A method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a reverse damascene in the formation of the conductive lines and vias. A conductive line pattern is first used to etch completely through the layer to form conductive line openings. The openings are completely filled with a conductive material and planarized so that the surfaces of the conductive material and the insulating layer are coplanar. A via pattern is aligned perpendicular to the conductive lines and the conductive material is etched half way through the conductive lines in other than the areas covered by the via pattern. The openings thus created in the upper portion of the conductive lines are filled with insulating material to complete the dual damascene interconnection level with the conductive lines in the lower portion of the insulating layer and upwardly projecting vias in the upper portion of the layer. In addition, a triple damascene layer is formed by starting with an insulating layer about one-third thicker than normal and by combining the standard dual damascene method with the above described method. The resulting interconnection level structure comprises conductive lines having upwardly and downwardly projecting vias.

摘要翻译： 一种制造导线的互连电平的方法，以及用于集成电路的绝缘和用于半导体器件的衬底载体分离的通孔的方法，其使用反向镶嵌来形成导电线和通孔。 首先使用导电线图案来完全蚀刻该层以形成导电线开口。 开口完全被导电材料填充并平坦化，使得导电材料和绝缘层的表面是共面的。 通孔图案垂直于导电线对齐，并且导电材料被除了通孔图案覆盖的区域之外的一半蚀刻通过导电线。 由此在导电线的上部形成的开口用绝缘材料填充，以完成与绝缘层下部的导电线和层的上部向上突出的通孔的双镶嵌互连水平。 此外，通过从绝对层开始比正常厚约三分之一的厚度并通过将标准双镶嵌方法与上述方法组合来形成三镶嵌层。 所产生的互连级联结构包括具有向上和向下突出的通孔的导线。