公开(公告)号：US10049927B2

公开(公告)日：2018-08-14

申请号：US15332737

申请日：2016-10-24

Applicant: Applied Materials, Inc.

Inventor： Bencherki Mebarki ,  Sean Kang ,  Keith Tatseun Wong ,  He Ren ,  Mehul B. Naik ,  Ellie Y. Yieh ,  Srinivas D. Nemani

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/532

Abstract: Aspects of the disclosure include methods of treating a substrate to remove one or more of voids, seams, and grain boundaries from interconnects formed on the substrate. The method includes heating the substrate in an environment pressurized at supra-atmospheric pressure. In one example, the substrate may be heated in a hydrogen-containing atmosphere.

公开(公告)号：US09911594B2

公开(公告)日：2018-03-06

申请号：US15346306

申请日：2016-11-08

Applicant: Applied Materials, Inc.

Inventor： Srinivas D. Nemani ,  Ellie Y. Yieh ,  Ludovic Godet ,  Yin Fan

IPC: H01L21/31 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3115 ,  H01J37/32

CPC classification number: H01L21/02304 ,  H01J37/32357 ,  H01J37/32403 ,  H01J37/32422 ,  H01L21/0228 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/31155 ,  H01L29/66795 ,  H01L29/66803

Abstract: Methods for forming fin structure with desired materials formed on different locations of the fin structure using a selective deposition process for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips are provided. In one embodiment, a method of forming a structure with desired materials on a substrate includes forming a patterned self-assembled monolayer on a circumference of a structure formed on a substrate, wherein the patterned self-assembled monolayer includes a treated layer formed among a self-assembled monolayer, and performing an atomic layer deposition process to form a material layer predominantly on the self-assembled monolayer from the patterned self-assembled monolayer.

公开(公告)号：US09852916B2

公开(公告)日：2017-12-26

申请号：US15194456

申请日：2016-06-27

Applicant: Applied Materials, Inc.

Inventor： Hao Chen ,  Chentsau (Chris) Ying ,  Srinivas D. Nemani ,  Ellie Y. Yieh

IPC: H01L21/308 ,  C23C16/34 ,  C23C16/455 ,  C23C16/50 ,  H01J37/32 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/67 ,  H01L21/677 ,  H01L21/033 ,  H01L21/3213 ,  C23C16/04 ,  H01L21/28

CPC classification number: H01L21/3086 ,  C23C16/04 ,  C23C16/34 ,  C23C16/345 ,  C23C16/45544 ,  C23C16/50 ,  H01J37/32009 ,  H01J37/32082 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/32139 ,  H01L21/67069 ,  H01L21/67207 ,  H01L21/67742

Abstract: A first portion of a multiple cycle spacer is formed on a sidewall of a patterned feature over a substrate. A spacer layer is deposited on the first portion using a first plasma process. The spacer layer is etched to form a second portion of the multiple cycle spacer on the first portion using a second plasma process. A cycle comprising depositing and etching of the spacer layer is continuously repeated until the multiple cycle spacer is formed.

公开(公告)号：US09379021B2

公开(公告)日：2016-06-28

申请号：US14505167

申请日：2014-10-02

Applicant: Applied Materials, Inc.

Inventor： Ellie Y. Yieh ,  Ludovic Godet ,  Srinivas D. Nemani

IPC: B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  H01L21/302 ,  H01L21/461 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/28 ,  H01L21/04 ,  H01L21/225 ,  H01L21/3115 ,  H01L21/223

CPC classification number: H01L21/823462 ,  H01L21/0415 ,  H01L21/046 ,  H01L21/2236 ,  H01L21/2253 ,  H01L21/28185 ,  H01L21/31155 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/66803 ,  H01L29/6681 ,  H01L29/785

Abstract: Embodiments described herein generally relate to methods for forming gate structures. Various processes may be performed on a gate dielectric material to reduce the K value of the dielectric material. The gate dielectric having a reduced K value may provide for reduced parasitic capacitance and an overall reduced capacitance. The gate dielectric may be modified without thermodynamic constraint.

Abstract translation: 本文描述的实施例通常涉及用于形成栅极结构的方法。 可以在栅极电介质材料上进行各种工艺以降低电介质材料的K值。 具有减小的K值的栅极电介质可以提供减小的寄生电容和整体减小的电容。 可以在没有热力学约束的情况下修改栅极电介质。

公开(公告)号：US20250133730A1

公开(公告)日：2025-04-24

申请号：US18919189

申请日：2024-10-17

Applicant: Applied Materials, Inc.

Inventor： WanGee Kim ,  Michel Frei ,  Mahendra Pakala ,  Ellie Y. Yieh

IPC: H10B12/00

Abstract: This specification describes technologies for creating and coupling word lines of a 3D memory cell array to corresponding word lines of a word line connect area. One aspect is a method that includes positioning a memory cell array on a substrate adjacent to a word line connect area, the word line connect area comprising a plurality of layers, the plurality of layers alternating between a first material and a second material; replacing at least a portion of the layers of the first material with a third material; and replacing at least a portion of the layers of the second material with a fourth material, wherein the fourth material forms word lines within the word line connect area and is electrically coupled to memory cell word lines within the memory cell array.

公开(公告)号：US12181801B2

公开(公告)日：2024-12-31

申请号：US17531108

申请日：2021-11-19

Applicant: Applied Materials, Inc.

Inventor： Dmitry Lubomirsky ,  Douglas A. Buchberger, Jr. ,  Qiwei Liang ,  Hyunjun Kim ,  Ellie Y. Yieh

IPC: G03F7/38 ,  H01J37/32

Abstract: A method and apparatus for performing post-exposure bake operations is described herein. The apparatus includes a plate stack and enables formation of a first high ion density plasma before the ion concentration within the first high ion density plasma is reduced using a diffuser to form a second low ion density plasma. The second low ion density plasma is an electron cloud or a dark plasma. An electric field is formed between a substrate support and the diffuser and through the second low ion density plasma during post-exposure bake of a substrate disposed on the substrate support. The second low ion density plasma electrically couples the substrate support and the diffuser during application of the electric field. The plate stack is equipped with power supplies and insulators to enable the formation or modification of a plasma within three regions of a process chamber.

公开(公告)号：US12085858B2

公开(公告)日：2024-09-10

申请号：US16825388

申请日：2020-03-20

Applicant: Applied Materials, Inc.

Inventor： Huixiong Dai ,  Srinivas D. Nemani ,  Steven Hiloong Welch ,  Mangesh Ashok Bangar ,  Ellie Y. Yieh

IPC: G03F7/20 ,  G03F7/16 ,  G03F7/38 ,  H01L21/027 ,  H01L21/266 ,  H01L21/311

CPC classification number: G03F7/20 ,  G03F7/16 ,  G03F7/38 ,  H01L21/0273 ,  H01L21/266 ,  H01L21/31133

Abstract: A method for enhancing a photoresist profile control includes applying a photoresist layer comprising a photoacid generator on an underlayer disposed on a material layer, exposing a first portion of the photoresist layer unprotected by a photomask to light radiation in a lithographic exposure process, providing a thermal energy to the photoresist layer in a post-exposure baking process, applying an electric field or a magnetic field while performing the post-exposure baking process, and drifting photoacid from the photoresist layer to a predetermined portion of the underlayer under the first portion of the photoresist layer.

公开(公告)号：US20240120195A1

公开(公告)日：2024-04-11

申请号：US17960979

申请日：2022-10-06

Applicant: Applied Materials, Inc. ,  Regents of the University of California

Inventor： Keith T. Wong ,  Srinivas D. Nemani ,  Ellie Y. Yieh ,  Andrew C. Kummel ,  Yunil Cho ,  James Huang

IPC: H01L21/02 ,  H01L21/67

CPC classification number: H01L21/0228 ,  H01L21/02068 ,  H01L21/02123 ,  H01L21/02304 ,  H01L21/02312 ,  H01L21/67017

Abstract: A method includes forming a conductive material on a first dielectric layer, exposing the conductive material to aniline to produce a passivated surface of the conductive material, and after exposing the conductive material to aniline, forming a second dielectric layer on the first dielectric layer using a deposition process. The deposition process is a water-free and plasma-free deposition process, and the second dielectric layer does not form on the passivated surface of the conductive material.

公开(公告)号：US11914299B2

公开(公告)日：2024-02-27

申请号：US17898216

申请日：2022-08-29

Applicant: Applied Materials, Inc.

Inventor： Huixiong Dai ,  Mangesh Ashok Bangar ,  Srinivas D. Nemani ,  Christopher S. Ngai ,  Ellie Y. Yieh

IPC: G03F7/20 ,  H01L21/027 ,  G03F7/30 ,  G03F7/38 ,  G03F7/16

CPC classification number: G03F7/20 ,  G03F7/16 ,  G03F7/30 ,  G03F7/38 ,  H01L21/0274

Abstract: A method for enhancing the depth of focus process window during a lithography process includes applying a photoresist layer comprising a photoacid generator on a material layer disposed on a substrate, exposing a first portion of the photoresist layer unprotected by a photomask to light radiation in a lithographic exposure process, providing a thermal energy to the photoresist layer in a post-exposure baking process, applying an electric field or a magnetic field while performing the post-exposure baking process, and dynamically changing a frequency of the electric field as generated while providing the thermal energy to the photoresist layer.

公开(公告)号：US20240038527A1

公开(公告)日：2024-02-01

申请号：US17873597

申请日：2022-07-26

Applicant: Applied Materials, Inc.

Inventor： Bhargav S. Citla ,  Srinivas D. Nemani ,  Purvam Modi ,  Ellie Y. Yieh

IPC: H01L21/02 ,  H01L21/321 ,  H01L21/3065

CPC classification number: H01L21/02274 ,  H01L21/3211 ,  H01L21/3065 ,  H01L21/02126

Abstract: A method includes depositing a flowable film on a substrate by providing a first input flow, the first input flow including plasma effluents of a first precursor, removing a portion of the flowable film from a sidewall of a feature defined within the substrate to obtain a remaining portion of the flowable film by providing a second input flow, the second input flow including plasma effluents of a second precursor, reducing hydrogen content of the remaining portion of the flowable film to obtain a densified film by providing a third input flow, the third input flow including plasma effluents of a third precursor, and treating the densified film in accordance with a film treatment process.