公开(公告)号：US06946704B2

公开(公告)日：2005-09-20

申请号：US10808510

申请日：2004-03-25

申请人： Hideyuki Matsuoka ,  Kiyoo Itoh ,  Motoyasu Terao ,  Satoru Hanzawa ,  Takeshi Sakata

发明人： Hideyuki Matsuoka ,  Kiyoo Itoh ,  Motoyasu Terao ,  Satoru Hanzawa ,  Takeshi Sakata

IPC分类号： G11C13/00 ,  H01L27/10 ,  H01L27/105 ,  H01L27/24 ,  H01L45/00 ,  H01L29/26

CPC分类号： H01L27/2454 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

摘要： A semiconductor memory cell and forming method thereof utilizes a vertical select transistor to eliminate the problem of a large cell surface area in memory cells of the related art utilizing phase changes. A memory cell with a smaller surface area than the DRAM device of the related art is achieved by the present invention. Besides low power consumption during read operation, the invention also provides phase change memory having low power consumption even during write operation. Phase change memory also has stable read-out operation.

摘要翻译： 半导体存储单元及其形成方法利用垂直选择晶体管来消除利用相位变化的现有技术的存储单元中的大的单元表面积的问题。 通过本发明实现了具有比现有技术的DRAM器件更小的表面积的存储单元。 除了读取操作中的低功耗之外，本发明还提供即使在写入操作期间具有低功耗的相变存储器。 相变存储器也具有稳定的读出操作。

公开(公告)号：US06917552B2

公开(公告)日：2005-07-12

申请号：US10671464

申请日：2003-09-29

申请人： Riichiro Takemura ,  Tomonori Sekiguchi ,  Takeshi Sakata

发明人： Riichiro Takemura ,  Tomonori Sekiguchi ,  Takeshi Sakata

IPC分类号： G11C7/00 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/4097

CPC分类号： G11C7/062 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4097

摘要： Disclosed is a sense amplifier arrangement that achieves high-speed access and shorter cycle time when array voltage is lowered in a DRAM. In a TG clocking sense system to separate data lines between the array side and the sense amplifier side in an early stage of a sensing period, a restore amplifier RAP is added, which amplifies data lines on the array side by referring to the data in the sense amplifier, and the restore amplifier is driven by a voltage VDH higher than the array voltage VDL. As a result, high-speed sense operation of the TG clocking system is made compatible with high-speed restore operation of overdrive system, and it is possible to achieve high-speed access operation and shorter cycle time.

公开(公告)号：US20050146960A1

公开(公告)日：2005-07-07

申请号：US11048915

申请日：2005-02-03

申请人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata ,  Kazushige Ayukawa ,  Takayuki Kawahara

发明人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata ,  Kazushige Ayukawa ,  Takayuki Kawahara

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C11/401 ,  G11C11/404 ,  G11C11/409 ,  G11C11/4096 ,  G11C15/00

CPC分类号： G11C7/1051 ,  G11C5/025 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C11/405 ,  G11C11/4096 ,  G11C2207/107

摘要： A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.

摘要翻译： 采用具有随机访问的数据寄存器的单交叉存储单元阵列的DRAM，只要芯片被外部访问即可。 当记录在数据寄存器中的数据项被同时写入存储单元阵列时，对数据项进行编码。 当将数据项从存储单元阵列读入数据寄存器时，数据项被解码。 由于从读数导出的阵列噪声减小，因此边缘被增强。 另外，DRAM的存取时间也减少了。

公开(公告)号：US20050056876A1

公开(公告)日：2005-03-17

申请号：US10975494

申请日：2004-10-29

申请人： Shinichi Miyatake ,  Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata

发明人： Shinichi Miyatake ,  Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata

IPC分类号： G11C11/401 ,  G11C7/18 ,  G11C11/403 ,  G11C11/405 ,  G11C11/406 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/0328 ,  H01L31/119

CPC分类号： H01L27/108 ,  G11C7/18 ,  G11C11/403 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4097 ,  G11C2211/4013 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10897 ,  Y10S257/905 ,  Y10S257/906

摘要： A semiconductor memory device is provided which can achieve the high integration, ultra-high speed operation, and significant reduction of power consumption during the information holding time, by reducing the increase in the area of a memory cell and obtaining a period of the ultra-high speed readout time and ensuring a long refresh period at the time of the self refresh. A DRAM employing a one-intersection cell·two cells/bit method has a twin cell structure employing a one-intersection 6 F2 cell, the structure in which: memory cells are arranged at positions corresponding to all of the intersections between a bit-line pair and a word line; and when a half pitch of the word line is defined as F, a pitch of each bit line of the bit-line pair is larger than 2 F and smaller than 4 F. Further, an active region in the silicon substrate, on which a source, channel and drain of the transistor of each memory cell are formed, is obliquely formed relative to the direction of the bit-line pair.

摘要翻译： 提供一种半导体存储器件，其可以通过减少存储器单元的面积的增加并获得超宽带的周期，实现信息保持时间期间的高集成度，超高速度运行和功耗的显着降低， 高速读出时间，确保自刷新时间长的刷新周期。 采用单交点单元两个单元/位方法的DRAM具有采用单交叉6 F 2单元的双单元结构，其结构是：存储单元布置在对应于a 位线对和字线; 并且当字线的半间距被定义为F时，位线对的每个位线的间距大于2F且小于4F。另外，硅衬底中的有源区域 形成每个存储单元的晶体管的源极，沟道和漏极，相对于位线对的方向倾斜地形成。

公开(公告)号：US06862232B2

公开(公告)日：2005-03-01

申请号：US10726658

申请日：2003-12-04

申请人： Satoru Hanzawa ,  Takeshi Sakata

发明人： Satoru Hanzawa ,  Takeshi Sakata

IPC分类号： G11C11/15 ,  G11C5/00 ,  G11C7/00 ,  G11C11/00 ,  G11C11/16 ,  G11C11/34 ,  H01L27/22 ,  H01L31/0328

CPC分类号： G11C29/787 ,  G11C7/14 ,  G11C11/1673 ,  G11C11/1693

摘要： A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1” or “0”, arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing “0”, arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.

摘要翻译： 虚拟单元包括多个用于存储“1”或“0”的第一存储单元MC，其布置在多个字线WR0至WR7与多个第一数据线D0至D7之间的交点处，多个第一 用于存储“1”或“0”的虚拟单元MCH，布置在字线WR0至WR7和第一虚拟数据线之间的交点处，以及多个第二虚拟单元MCL，用于存储“0” 字线WR0〜WR7与第二伪数据线DD1的交点。

公开(公告)号：US06798005B2

公开(公告)日：2004-09-28

申请号：US10206215

申请日：2002-07-29

申请人： Shinichiro Kimura ,  Toshiaki Yamanaka ,  Kiyoo Itoh ,  Takeshi Sakata ,  Tomonori Sekiguchi ,  Hideyuki Matsuoka

发明人： Shinichiro Kimura ,  Toshiaki Yamanaka ,  Kiyoo Itoh ,  Takeshi Sakata ,  Tomonori Sekiguchi ,  Hideyuki Matsuoka

IPC分类号： H01L27108

CPC分类号： H01L27/10852 ,  H01L27/108 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/90

摘要： A capacitor consisting of a storage electrode (19), a capacitor dielectric film (20) and a plate electrode (21) is formed in a trench formed through dielectric films (6, 8, 10 and 12) stacked on a semiconductor substrate (1) and buried wiring layers (9 and 11) are formed under the capacitor. As the capacitor is formed not in the semiconductor substrate but over it, there is room in area in which the capacitor can be formed and the difficulty of forming wiring is reduced by using the wiring layers (9 and 11) for a global word line and a selector line. As the upper face of an dielectric film (32) which is in contact with the lower face of wiring (34) in a peripheral circuit area is extended into a memory cell area and is in contact with the side of the capacitor (33), step height between the peripheral circuit area and the memory cell area is remarkably reduced.

摘要翻译： 在由半导体衬底（1）上层叠的电介质膜（6,8,10和12）形成的沟槽中形成由存储电极（19），电容器电介质膜（20）和平板电极（21）构成的电容器 ）和埋入布线层（9和11）形成在电容器下面。 由于电容器不是形成在半导体衬底中而是在其上形成，因此通过使用用于全局字线的布线层（9和11），可以形成电容器并且难以形成布线的难度减小， 随着在外围电路区域中与布线（34）的下表面接触的电介质膜（32）的上表面延伸到存储单元区域中并与电容器的侧面接触 （33），外围电路区域和存储单元区域之间的台阶高度显着降低。

公开(公告)号：US06674117B2

公开(公告)日：2004-01-06

申请号：US09915588

申请日：2001-07-27

申请人： Kazuo Yano ,  Tomoyuki Ishii ,  Takashi Hashimoto ,  Koichi Seki ,  Masakazu Aoki ,  Takeshi Sakata ,  Yoshinobu Nakagome ,  Kan Takeuchi

发明人： Kazuo Yano ,  Tomoyuki Ishii ,  Takashi Hashimoto ,  Koichi Seki ,  Masakazu Aoki ,  Takeshi Sakata ,  Yoshinobu Nakagome ,  Kan Takeuchi

IPC分类号： H01L2976

CPC分类号： B82Y10/00 ,  G11C11/22 ,  G11C11/404 ,  G11C16/02 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/28 ,  G11C2216/06 ,  G11C2216/08 ,  H01L21/28273 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11551 ,  H01L27/1203 ,  H01L29/42328 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/7613 ,  H01L29/785 ,  H01L29/7888

摘要： A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.

公开(公告)号：US06576510B2

公开(公告)日：2003-06-10

申请号：US09826088

申请日：2001-04-05

申请人： Toshiaki Yamanaka ,  Shin' ichiro Kimura ,  Hideyuki Matsuoka ,  Tomonori Sekiguchi ,  Takeshi Sakata ,  Kiyoo Itoh

发明人： Toshiaki Yamanaka ,  Shin' ichiro Kimura ,  Hideyuki Matsuoka ,  Tomonori Sekiguchi ,  Takeshi Sakata ,  Kiyoo Itoh

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L21/32053 ,  H01L21/32134 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/535 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10888 ,  H01L28/60 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to the present invention, an overlay margin is secured for matching a wiring electrode 11 with a storage electrode 15 of a capacitor at their point of contact and the required area for a memory cell can be decreased by placing the plug electrode 11 of titanium nitride in the active region of a semiconductor substrate or over the gate electrode, reducing the size of the opening for passing the storage electrode 15 of the capacitor of a stacked structure, and decreasing the line width of a wiring electrode 13. By the common use of the above-mentioned plug electrodes in a CMISFET region in the peripheral circuit and in a memory cell of a static RAM, their circuit layouts can be made compact.

摘要翻译： 根据本发明，确保了覆盖边缘，用于使布线电极11与电容器的接触点处的存储电极15匹配，并且可以通过将氮化钛的插头电极11放置在存储单元的所需区域 在半导体基板的有源区域或栅电极的上方，减小用于使层叠结构的电容器的存储电极15通过的开口的尺寸，并且减小布线电极13的线宽。通过共同使用 外围电路中的CMISFET区域和静态RAM的存储单元中的上述插头电极，可以使其电路布局紧凑。

公开(公告)号：US06573586B2

公开(公告)日：2003-06-03

申请号：US10081537

申请日：2002-02-25

申请人： Takeshi Sakata ,  Satoru Hanzawa ,  Hideyuki Matsuoka ,  Katsuro Watanabe ,  Kenchi Ito

发明人： Takeshi Sakata ,  Satoru Hanzawa ,  Hideyuki Matsuoka ,  Katsuro Watanabe ,  Kenchi Ito

IPC分类号： H01L2900

CPC分类号： H01L27/226 ,  B82Y10/00 ,  G11C11/16

摘要： Disclosed are a fast, highly-integrated and highly-reliable magnetoresistive random access memory (MRAM) and a semiconductor device which uses the MRAM. The semiconductor device performs the read-out operation of the MRAM using memory cells for storing information by using a change in magnetoresistance of a magnetic tunnel junction (MTJ) element with a high S/N ratio. Each memory cell includes an MTJ element and a bipolar transistor. The read-out operation is carried out by selecting a word line, amplifying a current flowing in the MTJ element of a target memory cell by the bipolar transistor and outputting the amplified current to an associated read data line.

公开(公告)号：US06512714B2

公开(公告)日：2003-01-28

申请号：US09942558

申请日：2001-08-31

申请人： Satoru Hanzawa ,  Takeshi Sakata

发明人： Satoru Hanzawa ,  Takeshi Sakata

IPC分类号： G11C702

CPC分类号： G11C11/4099 ,  G11C7/14

摘要： There are provided a reference voltage generating method used for reading out operation of a memory cell having amplification ability, and a dummy cell. The memory cell is composed of a read NMOS transistor, a write transistor, and a coupled-capacitance. The dummy cell is made such that two memory cells are connected in series. The dummy cell is arranged at the most far end of each of the data lines against the sense amplifier. A reference voltage is generated by making a difference in an amount of current flowing in each of the read NMOS transistors of the memory cell and the dummy cell. As a result, DRAM showing a higher speed, a higher integration and a lower electrical power as compared with those of the prior art device can be realized.

摘要翻译： 提供了用于读出具有放大能力的存储单元的操作的参考电压产生方法和虚拟单元。 存储单元由读取NMOS晶体管，写入晶体管和耦合电容构成。 虚拟单元被制成使得两个存储单元串联连接。 每个数据线的最远端布置在相对于读出放大器的虚拟单元。 通过使存储单元的读取NMOS晶体管和虚设单元中的每一个中流动的电流量的差异来产生参考电压。 结果，可以实现与现有技术的装置相比显示更高速度，更高集成度和更低电力的DRAM。