公开(公告)号：US20060244092A1

公开(公告)日：2006-11-02

申请号：US11477958

申请日：2006-06-28

申请人： Lingyi Zheng ,  Er-Xuan Ping

发明人： Lingyi Zheng ,  Er-Xuan Ping

IPC分类号： H01L29/00

CPC分类号： H01L21/02175 ,  C23C16/34 ,  H01L21/022 ,  H01L21/02205 ,  H01L21/3141 ,  H01L21/76841 ,  H01L28/60

摘要： The invention encompasses methods of forming metal nitride proximate dielectric materials. The metal nitride comprises two portions, with one of the portions being nearer the dielectric material than the other. The portion of the metal nitride nearest the dielectric material is formed from a non-halogenated metal-containing precursor, and the portion of the metal nitride further from the dielectric material is formed from a halogenated metal-containing precursor. The methodology of the present invention can be utilized for forming capacitor constructions, with the portion of the metal nitride formed from the halogenated metal-containing precursor being incorporated into a capacitor electrode.

公开(公告)号：US20150093907A1

公开(公告)日：2015-04-02

申请号：US14044138

申请日：2013-10-02

申请人： Ellie YIEH ,  Ludovic Godet ,  Srinivas Nemani ,  Er-Xuan Ping ,  Gary Dickerson

发明人： Ellie YIEH ,  Ludovic Godet ,  Srinivas Nemani ,  Er-Xuan Ping ,  Gary Dickerson

IPC分类号： H01L21/02 ,  H01L21/67

CPC分类号： H01L21/02271 ,  C23C14/021 ,  C23C14/046 ,  C23C16/0227 ,  C23C16/045 ,  C23C16/45544 ,  C23C16/50 ,  H01J37/32009 ,  H01J2237/334 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02315 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/67017 ,  H01L21/67213 ,  H01L21/76224

摘要： Embodiments include methods and systems of 3D structure fill. In one embodiment, a method of filling a trench in a wafer includes performing directional plasma treatment with an ion beam at an angle with respect to a sidewall of the trench to form a treated portion of the sidewall and an untreated bottom of the trench. A material is deposited in the trench. The deposition rate of the material on the treated portion of the sidewall is different than a second deposition rate on the untreated bottom of the trench. In one embodiment, a method includes depositing a material on the wafer, filling a bottom of the trench and forming a layer on a sidewall of the trench and a top surface adjacent to the trench. The method includes etching the layer with an ion beam at an angle with respect to the sidewall.

摘要翻译： 实施例包括3D结构填充的方法和系统。 在一个实施例中，在晶片中填充沟槽的方法包括使用离子束相对于沟槽的侧壁以一定角度执行定向等离子体处理，以形成侧壁的处理部分和沟槽的未处理底部。 材料沉积在沟槽中。 材料在侧壁的处理部分上的沉积速率不同于沟槽的未处理底部上的第二沉积速率。 在一个实施例中，一种方法包括在晶片上沉积材料，填充沟槽的底部并在沟槽的侧壁上形成层，以及邻近沟槽的顶表面。 该方法包括用相对于侧壁成一定角度的离子束蚀刻该层。

公开(公告)号：US08551855B2

公开(公告)日：2013-10-08

申请号：US12834942

申请日：2010-07-13

申请人： Huiwen Xu ,  Er-Xuan Ping ,  Xiying Costa

发明人： Huiwen Xu ,  Er-Xuan Ping ,  Xiying Costa

IPC分类号： H01L21/20

CPC分类号： H01L45/1675 ,  H01L21/02115 ,  H01L21/02274 ,  H01L21/3146 ,  H01L21/32139 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/149 ,  H01L45/1616 ,  H01L45/1683

摘要： Memory cells, and methods of forming such memory cells, are provided that include a steering element coupled to a carbon-based reversible resistivity switching material that has an increased resistivity, and a switching current that is less than a maximum current capability of the steering element used to control current flow through the carbon-based reversible resistivity switching material. In particular embodiments, methods and apparatus in accordance with this invention form a steering element, such as a diode, having a first width, coupled to a reversible resistivity switching material, such as aC, having a second width smaller than the first width.

摘要翻译： 提供了存储单元和形成这种存储单元的方法，其包括耦合到具有增加的电阻率的碳基可逆电阻率切换材料的转向元件和小于转向元件的最大电流能力的开关电流 用于控制通过碳基可逆电阻率开关材料的电流。 在具体实施例中，根据本发明的方法和装置形成具有第一宽度的转向元件，例如二极管，该第二宽度与第二宽度小于第一宽度的可逆电阻率开关材料（例如aC）耦合。

公开(公告)号：US08440567B2

公开(公告)日：2013-05-14

申请号：US13033268

申请日：2011-02-23

申请人： Junting Liu ,  Er-Xuan Ping ,  Seiichi Takedai

发明人： Junting Liu ,  Er-Xuan Ping ,  Seiichi Takedai

IPC分类号： H01L21/302

CPC分类号： H01L21/768 ,  C23C18/1605 ,  C25D5/022 ,  C25D7/12 ,  H01L21/56 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/056 ,  H01L2224/05664 ,  H01L2224/131 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/01028 ,  H01L2924/00

摘要： Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a plating bath to grow conductive contact regions within the openings. The insulative material across the back side may protect the back side from being plated during the growth of the conductive contact regions over the front side. In some embodiments, plasma-enhanced atomic layer deposition may be utilized for the deposition, and may be conducted at a temperature suitable to anneal passivation materials so that such annealing occurs simultaneously with the plasma-enhanced atomic layer deposition.

摘要翻译： 一些实施方案包括其中绝缘材料同时沉积在半导体衬底的正面和跨衬底背面的方法。 随后，穿过前侧的绝缘材料可以蚀刻开口，然后可以将衬底浸入镀浴中，以在开口内增长导电接触区域。 跨越背面的绝缘材料可以在导电接触区域在前侧的生长期间保护背面免受电镀。 在一些实施例中，等离子体增强的原子层沉积可以用于沉积，并且可以在适于退火钝化材料的温度下进行，使得这种退火与等离子体增强的原子层沉积同时发生。

公开(公告)号：US20120193756A1

公开(公告)日：2012-08-02

申请号：US13020007

申请日：2011-02-02

申请人： Steven Maxwell ,  Abhijit Bandyopadhyay ,  Kun Hou ,  Er-Xuan Ping ,  Yung-Tin Chen ,  Li Xiao

发明人： Steven Maxwell ,  Abhijit Bandyopadhyay ,  Kun Hou ,  Er-Xuan Ping ,  Yung-Tin Chen ,  Li Xiao

IPC分类号： H01L29/861 ,  H01L21/36 ,  H01L29/92

CPC分类号： H01L27/1021 ,  H01L29/868 ,  Y10S438/90

摘要： In a first aspect, a vertical semiconductor diode is provided that includes (1) a first semiconductor layer formed above a substrate; (2) a second semiconductor layer formed above the first semiconductor layer; (3) a first native oxide layer formed above the first semiconductor layer; and (4) a third semiconductor layer formed above the first semiconductor layer, second semiconductor layer and first native oxide layer so as to form the vertical semiconductor diode that includes the first native oxide layer. Numerous other aspects are provided.

摘要翻译： 在第一方面，提供一种垂直半导体二极管，其包括：（1）形成在基板上的第一半导体层; （2）形成在第一半导体层上方的第二半导体层; （3）形成在所述第一半导体层上方的第一自然氧化物层; 以及（4）形成在第一半导体层上的第三半导体层，第二半导体层和第一自然氧化物层，以形成包括第一自然氧化物层的垂直半导体二极管。 提供了许多其他方面。

公开(公告)号：US08093123B2

公开(公告)日：2012-01-10

申请号：US12541075

申请日：2009-08-13

申请人： Huiwen Xu ,  Er-Xuan Ping

发明人： Huiwen Xu ,  Er-Xuan Ping

IPC分类号： H01L21/8242

CPC分类号： H01L27/101 ,  H01L27/1021 ,  H01L27/1052

摘要： Methods of forming memory cells are disclosed which include forming a pillar above a substrate, the pillar including a steering element and a memory element, and performing one or more etches vertically through the pillar to form multiple memory cells. Memory cells formed from such methods, as well as numerous other aspects are also disclosed.

摘要翻译： 公开了形成存储器单元的方法，其包括在衬底上形成柱，所述柱包括转向元件和存储元件，并且通过柱垂直地执行一个或多个蚀刻以形成多个存储单元。 还公开了由这些方法形成的存储单元以及许多其它方面。

公开(公告)号：US20090257265A1

公开(公告)日：2009-10-15

申请号：US12153872

申请日：2008-05-27

申请人： Xiying Chen ,  Bing K. Yen ,  Dat Nguyen ,  Huiwen Xu ,  George Samachisa ,  Tanmay Kumar ,  Er-Xuan Ping

发明人： Xiying Chen ,  Bing K. Yen ,  Dat Nguyen ,  Huiwen Xu ,  George Samachisa ,  Tanmay Kumar ,  Er-Xuan Ping

IPC分类号： G11C11/00 ,  G11C11/34 ,  G11C7/00

CPC分类号： G11C11/56 ,  B82Y10/00 ,  G11C13/00 ,  G11C13/0069 ,  G11C13/025 ,  G11C2013/009 ,  G11C2213/35 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/149 ,  H01L45/1616 ,  H01L45/1675

摘要： A nonvolatile memory cell includes a steering element located in series with a storage element. The storage element includes a carbon material and the memory cell includes a rewritable cell having multiple memory levels.

摘要翻译： 非易失性存储单元包括与存储元件串联定位的转向元件。 存储元件包括碳材料，并且存储单元包括具有多个存储器级别的可重写单元。

公开(公告)号：US07268382B2

公开(公告)日：2007-09-11

申请号：US11449433

申请日：2006-06-07

申请人： Shenlin Chen ,  Trung Tri Doan ,  Guy T. Blalock ,  Lyle D. Breiner ,  Er-Xuan Ping

发明人： Shenlin Chen ,  Trung Tri Doan ,  Guy T. Blalock ,  Lyle D. Breiner ,  Er-Xuan Ping

IPC分类号： H01L29/72

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/84 ,  Y10S438/964

摘要： The invention includes a method of forming a rugged semiconductor-containing surface. A first semiconductor layer is formed over a substrate, and a second semiconductor layer is formed over the first semiconductor layer. Subsequently, a third semiconductor layer is formed over the second semiconductor layer, and semiconductor-containing seeds are formed over the third semiconductor layer. The seeds are annealed to form the rugged semiconductor-containing surface. The first, second and third semiconductor layers are part of a common stack, and can be together utilized within a storage node of a capacitor construction. The invention also includes semiconductor structures comprising rugged surfaces. The rugged surfaces can be, for example, rugged silicon.

摘要翻译： 本发明包括形成坚固的含半导体的表面的方法。 在衬底上形成第一半导体层，并且在第一半导体层上形成第二半导体层。 随后，在第二半导体层上形成第三半导体层，并且在第三半导体层上形成含半导体的种子。 将种子退火以形成坚固的含半导体的表面。 第一，第二和第三半导体层是公共堆叠的一部分，并且可以在电容器结构的存储节点内一起使用。 本发明还包括包括粗糙表面的半导体结构。 坚固的表面可以是例如坚固的硅。

公开(公告)号：US07247581B2

公开(公告)日：2007-07-24

申请号：US11206340

申请日：2005-08-17

申请人： Trung Tri Doan ,  Lyle D. Breiner ,  Er-Xuan Ping ,  Lingyi A. Zheng

发明人： Trung Tri Doan ,  Lyle D. Breiner ,  Er-Xuan Ping ,  Lingyi A. Zheng

IPC分类号： H01L21/31

CPC分类号： H01L21/0228 ,  C23C16/0236 ,  C23C16/0245 ,  C23C16/45546 ,  C23C16/54 ,  C30B25/02 ,  H01L21/02046 ,  H01L21/0214 ,  H01L21/02142 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02175 ,  H01L21/02211 ,  H01L21/02326 ,  H01L21/28562 ,  H01L21/3144 ,  H01L21/31604 ,  H01L21/31683 ,  H01L21/3185 ,  H01L21/76841 ,  H01L21/76856 ,  H01L21/76888

摘要： The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the native oxide, the substrates are simultaneously exposed to a first reactive material to form a first mass across at least some exposed surfaces of the substrates. The first reactive material is removed from the reaction chamber, and subsequently the substrates are exposed to a second reactive material to convert the first mass to a second mass. The invention also includes apparatuses which can be utilized for simultaneous ALD treatment of a plurality of discrete semiconductor substrates.

摘要翻译： 本发明包括用于处理多个分立半导体衬底的方法。 离散的半导体衬底被放置在反应室内。 当衬底在室内时，它们同时暴露于H，F和Cl中的一种或多种以除去天然氧化物。 在除去天然氧化物之后，将基板同时暴露于第一反应性材料，以在基底的至少一些暴露表面上形成第一质量。 将第一反应性材料从反应室中除去，随后将基板暴露于第二反应性材料以将第一质量转化为第二质量。 本发明还包括可以用于多个分立半导体衬底的同时ALD处理的装置。

公开(公告)号：US07244648B2

公开(公告)日：2007-07-17

申请号：US11375696

申请日：2006-03-13

申请人： Er-Xuan Ping ,  Zhiping Yin

发明人： Er-Xuan Ping ,  Zhiping Yin

IPC分类号： H01L21/8234

CPC分类号： H01L21/0217 ,  C23C16/345 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/3185 ,  H01L27/10808 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/84 ,  H01L28/91 ,  H01L29/945

摘要： The invention encompasses a method of forming a silicon nitride layer. A substrate is provided which comprises a first mass and a second mass. The first mass comprises silicon and the second mass comprises silicon oxide. A sacrificial layer is formed over the first mass. While the sacrificial layer is over the first mass, a nitrogen-containing material is formed across the second mass. After the nitrogen-containing material is formed, the sacrificial layer is removed. Subsequently, a silicon nitride layer is formed to extend across the first and second masses, with the silicon nitride layer being over the nitrogen-containing material. Also, a conductivity-enhancing dopant is provided within the first mass. The invention also pertains to methods of forming capacitor constructions.

摘要翻译： 本发明包括形成氮化硅层的方法。 提供了包括第一质量和第二质量的衬底。 第一质量包括硅，第二质量包含氧化硅。 在第一质量块上形成牺牲层。 当牺牲层超过第一质量时，在第二质量块上形成含氮材料。 在形成含氮材料之后，去除牺牲层。 随后，形成氮化硅层以跨越第一和第二质量块延伸，其中氮化硅层在含氮材料之上。 此外，在第一质量块内提供导电性增强掺杂剂。 本发明还涉及形成电容器结构的方法。