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102 条记录 (耗时 0.025 秒)

    FUNNELED LIGHT PIPE FOR PIXEL SENSORS
    41.
    发明申请
    FUNNELED LIGHT PIPE FOR PIXEL SENSORS 有权
    用于像素传感器的FUNNELED LIGHT PIPE

    公开(公告)号：US20070138380A1

    公开(公告)日：2007-06-21

    申请号：US11275171

    申请日：2005-12-16

    申请人： James Adkisson ,  Jeffrey Gambino ,  Robert Leidy ,  Richard Rassel

    发明人： James Adkisson ,  Jeffrey Gambino ,  Robert Leidy ,  Richard Rassel

    IPC分类号： G01J1/04

    CPC分类号： G01J1/04 ,  G01J1/0407 ,  G01J1/0422 ,  G01J1/0488

    摘要： A photo sensing structure and methods for forming the same. The structure includes (a) a semiconductor substrate and (b) a photo collection region on the semiconductor substrate. The structure also includes a funneled light pipe on top of the photo collection region. The funneled light pipe includes (i) a bottom cylindrical portion on top of the photo collection region of the photo collection region, and (ii) a funneled portion which has a tapered shape and is on top and in direct physical contact with the bottom cylindrical portion. The structure further includes a color filter region on top of the funneled light pipe.

    摘要翻译： 感光结构及其形成方法。 该结构包括（a）半导体衬底和（b）半导体衬底上的光收集区域。 该结构还包括在照片收集区域顶部的漏斗光管。 漏斗式光管包括（i）照片收集区域的照片收集区域顶部的底部圆柱形部分，和（ii）具有锥形形状并且在顶部并与底部圆柱体直接物理接触的漏斗部分 一部分。 该结构还包括在漏斗的光管的顶部上的滤色器区域。

    LIGHT SHIELD FOR CMOS IMAGER
    42.
    发明申请
    LIGHT SHIELD FOR CMOS IMAGER 有权
    CMOS成像器的光栅

    公开(公告)号：US20070102738A1

    公开(公告)日：2007-05-10

    申请号：US11164072

    申请日：2005-11-09

    申请人： James Adkisson ,  Jeffrey Gambino ,  Mark Jaffe

    发明人： James Adkisson ,  Jeffrey Gambino ,  Mark Jaffe

    IPC分类号： H01L31/113 ,  H01L31/062

    CPC分类号： H01L27/14623 ,  H01L27/14685

    摘要： The present invention provides a light shield for shielding the floating diffusion of a complementary metal-oxide semiconductor (CMOS) imager. In accordance with an embodiment of the present invention, there is provided a pixel sensor cell including: a device region formed on a substrate; and a first layer of material forming a sidewall adjacent to a side of the device region for blocking electromagnetic radiation from the device region.

    摘要翻译： 本发明提供一种用于屏蔽互补金属氧化物半导体（CMOS）成像器的浮动扩散的遮光罩。 根据本发明的实施例，提供了一种像素传感器单元，包括：形成在基板上的器件区域; 以及形成与所述器件区域的一侧相邻的侧壁的第一材料层，用于阻挡来自所述器件区域的电磁辐射。

    High performance embedded dram technology with strained silicon
    44.
    发明申请
    High performance embedded dram technology with strained silicon 失效
    具有应变硅的高性能嵌入式显示技术

    公开(公告)号：US20060024877A1

    公开(公告)日：2006-02-02

    申请号：US10541660

    申请日：2003-01-08

    申请人： Jack Mandelman ,  Jeffrey Gambino ,  Geng Wang

    发明人： Jack Mandelman ,  Jeffrey Gambino ,  Geng Wang

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/10894 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/3081 ,  H01L27/10864

    摘要： Semiconductor devices are fabricated in a strained layer region and strained layer-free region of the same substrate. A first semiconductor device, such as a memory cell, e.g. a deep trench storage cell, is formed in a strained layer-free region of the substrate. A strained layer region is selectively formed in the same substrate. A second semiconductor device (66, 68, 70), such as an FET, e.g. an MOSFET logic device, is formed in the strained layer region.

    摘要翻译： 半导体器件制造在同一衬底的应变层区域和无应变层的层中。 第一半导体器件，例如存储器单元，例如 在衬底的无应变层的区域中形成深沟槽存储单元。 在相同的衬底中选择性地形成应变层区域。 第二半导体器件（66,68,70），例如FET，例如， 一个MOSFET逻辑器件，形成在应变层区域中。

    METAL-INSULATOR-METAL CAPACITOR AND METHOD OF FABRICATION
    46.
    发明申请
    METAL-INSULATOR-METAL CAPACITOR AND METHOD OF FABRICATION 有权
    金属绝缘体 - 金属电容器和制造方法

    公开(公告)号：US20050067701A1

    公开(公告)日：2005-03-31

    申请号：US10605444

    申请日：2003-09-30

    申请人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Zhong-Xiang He ,  Vidhya Ramachandran

    发明人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Zhong-Xiang He ,  Vidhya Ramachandran

    IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L23/52 ,  H01L21/44

    CPC分类号： H01L21/7687 ,  H01L23/5223 ,  H01L23/53238 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method and structure for a MIM capacitor, the structure including: an electronic device, comprising: an interlevel dielectric layer formed on a semiconductor substrate; a copper bottom electrode formed in the interlevel dielectric layer, a top surface of the bottom electrode co-planer with a top surface of the interlevel dielectric layer; a conductive diffusion barrier in direct contact with the top surface of the bottom electrode; a MIM dielectric in direct contact with a top surface of the conductive diffusion barrier; and a top electrode in direct contact with a top surface of the MIM dielectric. The conductive diffusion barrier may be recessed into the copper bottom electrode or an additional recessed conductive diffusion barrier provided. Compatible resistor and alignment mark structures are also disclosed.

    摘要翻译： 一种MIM电容器的方法和结构，该结构包括：电子器件，包括：形成在半导体衬底上的层间电介质层; 形成在所述层间电介质层中的铜底电极，所述底电极共平面的上表面与所述层间电介质层的顶面形成; 与底部电极的顶表面直接接触的导电扩散阻挡层; 与所述导电扩散阻挡层的顶表面直接接触的MIM电介质; 以及与MIM电介质的顶表面直接接触的顶部电极。 导电扩散阻挡层可以凹进到铜底电极或设置的另外的凹入的导电扩散阻挡层中。 还公开了兼容的电阻器和对准标记结构。

    Pixel sensor cell having asymmetric transfer gate with reduced pinning layer barrier potential
    48.
    发明授权
    Pixel sensor cell having asymmetric transfer gate with reduced pinning layer barrier potential 有权
    具有不对称传输门的像素传感器单元具有降低的钉扎层屏障电势

    公开(公告)号：US07528427B2

    公开(公告)日：2009-05-05

    申请号：US11668555

    申请日：2007-01-30

    申请人： Jeffrey Gambino ,  Mark Jaffe

    发明人： Jeffrey Gambino ,  Mark Jaffe

    IPC分类号： H01L31/062 ,  H01L27/148

    CPC分类号： H01L27/14603 ,  H01L27/14609 ,  H01L27/1463

    摘要： A pixel sensor cell structure and method of manufacture. Disclosed is a pixel sensor cell comprising an asymmetric transfer gate for providing a pinning layer having an edge spaced a further distance from the gate channel region than an edge of a charge collection well. Potential barrier interference to charge transfer caused by the pinning layer is reduced.

    摘要翻译： 像素传感器单元结构及其制造方法。 公开了一种像素传感器单元，其包括非对称传输门，用于提供钉扎层，该钉扎层的边缘与电荷收集阱的边缘相距离栅极沟道区域的距离更远。 降低了由钉扎层引起的电荷转移的电位障碍。

    LOW LEAKAGE METAL-CONTAINING CAP PROCESS USING OXIDATION
    50.
    发明申请
    LOW LEAKAGE METAL-CONTAINING CAP PROCESS USING OXIDATION 失效
    使用氧化的低泄漏金属包覆工艺

    公开(公告)号：US20070235875A1

    公开(公告)日：2007-10-11

    申请号：US11279019

    申请日：2006-04-07

    申请人： Jeffrey Gambino ,  Jason Gill ,  Sean Smith ,  Jean Wynne

    发明人： Jeffrey Gambino ,  Jason Gill ,  Sean Smith ,  Jean Wynne

    IPC分类号： H01L23/52

    CPC分类号： H01L23/53238 ,  H01L21/288 ,  H01L21/76829 ,  H01L21/76849 ,  H01L21/76856 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An interconnect structure which includes a metal-containing cap located atop each conductive feature that is present within a dielectric material is provided in which a surface region of the metal-containing cap is oxidized prior to the subsequent deposition of any other dielectric material thereon. Moreover, metal particles that are located on the surface of the dielectric material between the conductive features are also oxidized at the same time as the surface region of the metal-containing cap. This provides a structure having a reduced leakage current. In accordance with the present invention, the oxidation step is performed after electroless plating of the metal-containing cap and prior to the deposition of a dielectric capping layer or an overlying interlayer or intralevel dielectric material.

    摘要翻译： 提供一种互连结构，其包括位于电介质材料内部的每个导电特征顶部的位于金属的盖的顶盖，其中含金属盖的表面区域在其后沉积任何其它电介质材料之前被氧化。 此外，位于介电材料表面之间的导电特征之间的金属颗粒也与含金属盖的表面区域同时被氧化。 这提供了具有减小的漏电流的结构。 根据本发明，氧化步骤是在含金属盖的无电镀之后并且在沉积介电覆盖层或上覆的中间层或电介质材料之前进行的。