公开(公告)号：US20060172514A1

公开(公告)日：2006-08-03

申请号：US10906013

申请日：2005-01-31

申请人： Jeffrey Gambino ,  Anthony Stamper

发明人： Jeffrey Gambino ,  Anthony Stamper

IPC分类号： H01L21/425 ,  H01L21/461

CPC分类号： H01L21/7684 ,  H01J2237/0812 ,  H01L21/32115 ,  H01L21/32136 ,  Y10S438/961

摘要： A damascene process incorporating a GCIB step is provided. The GCIB step can replace one or more CMP steps in the traditional damascene process. The GCIB step allows for selectable removal of unwanted material and thus, reduces unwanted erosion of certain nearby structures during damascene process. A GCIB step may also be incorporated in the damascene process as a final polish step to clean up surfaces that have been planarized using a CMP step.

摘要翻译： 提供了一个结合GCIB步骤的镶嵌工艺。 GCIB步骤可以替代传统镶嵌工艺中的一个或多个CMP步骤。 GCIB步骤允许选择性地去除不想要的材料，并因此减少镶嵌过程中某些附近结构的不必要的侵蚀。 GCIB步骤也可以作为最后抛光步骤结合在镶嵌工艺中，以清理已经使用CMP步骤进行平面化的表面。

公开(公告)号：US20060138480A1

公开(公告)日：2006-06-29

申请号：US10905277

申请日：2004-12-23

申请人： James Adkisson ,  Jeffrey Gambino ,  Mark Jaffe ,  Robert Leidy ,  Richard Rassel ,  Anthony Stamper

发明人： James Adkisson ,  Jeffrey Gambino ,  Mark Jaffe ,  Robert Leidy ,  Richard Rassel ,  Anthony Stamper

IPC分类号： H01L31/113 ,  H01L31/0232 ,  H01L31/00

CPC分类号： H01L27/14636 ,  H01L21/76819 ,  H01L21/76834 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14645 ,  H01L27/14683

摘要： An image sensor and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack to result in a pixel array exhibiting increased light sensitivity. The image sensor includes structures having a minimum thickness of barrier layer metal that traverses the optical path of each pixel in the sensor array or, that have portions of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer may be formed atop the Cu metallization by a self-aligned deposition.

摘要翻译： 一种图像传感器和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合较薄的层间电介质堆叠以产生呈现增加的光敏度的像素阵列。 图像传感器包括具有穿过传感器阵列中的每个像素的光路的阻挡层金属的最小厚度的结构，或者具有从每个像素的光路中选择性地去除的阻挡层金属的部分，从而使反射率最小化。 也就是说，通过实现各种块或单掩模方法，在阵列中的每个像素的光路的位置处完全去除了阻挡层金属的部分。 在另一个实施例中，阻挡金属层可以通过自对准沉积形成在Cu金属化之上。

公开(公告)号：US20060249848A1

公开(公告)日：2006-11-09

申请号：US10908346

申请日：2005-05-09

申请人： Douglas Coolbaugh ,  Daniel Edelstein ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Robert Rassel ,  Anthony Stamper

发明人： Douglas Coolbaugh ,  Daniel Edelstein ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Robert Rassel ,  Anthony Stamper

IPC分类号： B32B7/12

CPC分类号： H01L24/11 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05007 ,  H01L2224/05022 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05552

摘要： Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal pads subtractively or by a damascene process.

公开(公告)号：US20070059920A1

公开(公告)日：2007-03-15

申请号：US11555383

申请日：2006-11-01

申请人： Jeffrey Gambino ,  William Hill ,  Kenneth McAvey ,  Thomas McDevitt ,  Anthony Stamper ,  Arthur Winslow ,  Robert Zwonik

发明人： Jeffrey Gambino ,  William Hill ,  Kenneth McAvey ,  Thomas McDevitt ,  Anthony Stamper ,  Arthur Winslow ,  Robert Zwonik

IPC分类号： H01L21/4763

CPC分类号： H01L21/76832 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76834

摘要： An integrated circuit and a method of manufacturing the integrated circuit, the method including: (a) providing a substrate; (b) forming a copper diffusion barrier layer on the substrate; (c) forming a dielectric layer on a top surface of the copper diffusion barrier layer; (d) forming a copper damascene or dual damascene wire in the dielectric layer, a top surface of the copper damascene or dual damascene wire coplanar with a top surface of the dielectric layer; (e) forming a first capping layer on the top surface of the wire and the top surface of the dielectric layer; (f) after step (e) performing one or more characterization procedures in relation to said integrated circuit; and (g) after step (e) forming a second capping layer on a top surface of the first capping layer.

摘要翻译： 一种集成电路和集成电路的制造方法，所述方法包括：（a）提供衬底; （b）在所述基板上形成铜扩散阻挡层; （c）在铜扩散阻挡层的顶表面上形成电介质层; （d）在所述电介质层中形成铜镶嵌或双镶嵌线，所述铜镶嵌件的顶表面或与所述电介质层的顶表面共面的双镶嵌线; （e）在所述导线的顶表面和所述电介质层的顶表面上形成第一覆盖层; （f）在步骤（e）执行与所述集成电路相关的一个或多个表征程序之后; 和（g）在步骤（e）之后，在第一覆盖层的顶表面上形成第二覆盖层。

公开(公告)号：US20060063373A1

公开(公告)日：2006-03-23

申请号：US10711456

申请日：2004-09-20

申请人： Jeffrey Gambino ,  William Hill ,  Kenneth McAvey ,  Thomas McDevitt ,  Anthony Stamper ,  Arthur Winslow ,  Robert Zwonik

发明人： Jeffrey Gambino ,  William Hill ,  Kenneth McAvey ,  Thomas McDevitt ,  Anthony Stamper ,  Arthur Winslow ,  Robert Zwonik

IPC分类号： H01L21/4763

CPC分类号： H01L21/76832 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76834

摘要： An integrated circuit and a method of manufacturing the integrated circuit, the method including: (a) providing a substrate; (b) forming a copper diffusion barrier layer on the substrate; (c) forming a dielectric layer on a top surface of the copper diffusion barrier layer; (d) forming a copper damascene or dual damascene wire in the dielectric layer, a top surface of the copper damascene or dual damascene wire coplanar with a top surface of the dielectric layer; (e) forming a first capping layer on the top surface of the wire and the top surface of the dielectric layer; (f) after step (e) performing one or more characterization procedures in relation to said integrated circuit; and (g) after step (e) forming a second capping layer on a top surface of the first capping layer.

摘要翻译： 一种集成电路和集成电路的制造方法，所述方法包括：（a）提供衬底; （b）在所述基板上形成铜扩散阻挡层; （c）在铜扩散阻挡层的顶表面上形成电介质层; （d）在所述电介质层中形成铜镶嵌或双镶嵌线，所述铜镶嵌件的顶表面或与所述电介质层的顶表面共面的双镶嵌线; （e）在所述导线的顶表面和所述电介质层的顶表面上形成第一覆盖层; （f）在步骤（e）执行与所述集成电路相关的一个或多个表征程序之后; 和（g）在步骤（e）之后在第一盖层的顶表面上形成第二盖层。

公开(公告)号：US20050153505A1

公开(公告)日：2005-07-14

申请号：US10707811

申请日：2004-01-14

申请人： Jeffrey Gambino ,  Anthony Stamper

发明人： Jeffrey Gambino ,  Anthony Stamper

IPC分类号： H01L21/312 ,  H01L21/314 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/8238

CPC分类号： H01L21/02167 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/312 ,  H01L21/3121 ,  H01L21/3122 ,  H01L21/3148 ,  H01L21/31612 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The present invention provides a method of forming a rigid interconnect structure, and the device therefrom, including the steps of providing a lower metal wiring layer having first metal lines positioned within a lower low-k dielectric; depositing an upper low-k dielectric atop the lower metal wiring layer; etching at least one portion of the upper low-k dielectric to provide at least one via to the first metal lines; forming rigid dielectric sidewall spacers in at least one via of the upper low-k dielectric; and forming second metal lines in at least one portion of the upper low-k dielectric. The rigid dielectric sidewall spacers may comprise of SiCH, SiC, SiNH, SiN, or SiO2. Alternatively, the via region of the interconnect structure may be strengthened with a mechanically rigid dielectric comprising SiO2, SiCOH, or doped silicate glass.

摘要翻译： 本发明提供一种形成刚性互连结构及其装置的方法，包括以下步骤：提供具有位于下部低k电介质内的第一金属线的下金属布线层; 在下部金属布线层的顶部沉积上部低k电介质; 蚀刻上部低k电介质的至少一部分以向第一金属线提供至少一个通孔; 在所述上部低k电介质的至少一个通路中形成刚性电介质侧壁间隔物; 以及在所述上部低k电介质的至少一部分中形成第二金属线。 刚性电介质侧壁间隔物可以包括SiCH，SiC，SiNH，SiN或SiO 2。 或者，可以用包含SiO 2，SiCOH或掺杂硅酸盐玻璃的机械刚性电介质来加强互连结构的通孔区域。

公开(公告)号：US20080102543A1

公开(公告)日：2008-05-01

申请号：US11968686

申请日：2008-01-03

申请人： Arne Ballantine ,  Daniel Edelstein ,  Anthony Stamper

发明人： Arne Ballantine ,  Daniel Edelstein ,  Anthony Stamper

IPC分类号： H01L21/66 ,  H01L21/31

CPC分类号： C23C8/02 ,  C23C8/04 ,  C23C8/10 ,  C23C8/24 ,  C25D11/00 ,  C25D11/02 ,  C25D11/026 ,  H01C7/006 ,  H01C17/26 ,  H01L21/263 ,  H01L27/0802 ,  H01L29/8605 ,  Y10S257/904 ,  Y10S257/914

摘要： A method for increasing an electrical resistance of a resistor that is within a semiconductor structure. A fraction of a surface layer of the resistor is oxidized with oxygen particles. In an embodiment, the fraction of the surface layer is heated by a beam of particles, such that the semiconductor structure is within a chamber that includes the oxygen particles as gaseous oxygen-comprising molecules. In an embodiment, the semiconductor structure is immersed in a chemical solution which includes the oxygen particles, wherein the oxygen particles includes oxygen-comprising liquid molecules, oxygen ions, or an oxygen-comprising gas dissolved in the chemical solution under pressurization. In an embodiment, the resistor is tested to determine whether the electrical resistance of the resistor after being oxidized with the oxygen particles is within a tolerance of a predetermined target resistance.

摘要翻译： 一种用于增加在半导体结构内的电阻器的电阻的方法。 电阻的表面层的一部分被氧颗粒氧化。 在一个实施方案中，表面层的分数由颗粒束加热，使得半导体结构在包含作为气态含氧分子的氧颗粒的室内。 在一个实施方案中，将半导体结构浸入包括氧颗粒的化学溶液中，其中氧颗粒包括在加压下溶解在化学溶液中的含氧液体分子，氧离子或含氧气体。 在一个实施例中，测试电阻器以确定在用氧颗粒氧化后电阻器的电阻是否在预定目标电阻的容限内。

公开(公告)号：US20070267286A1

公开(公告)日：2007-11-22

申请号：US11836308

申请日：2007-08-09

申请人： Arne Ballantine ,  Daniel Edelstein ,  Anthony Stamper

发明人： Arne Ballantine ,  Daniel Edelstein ,  Anthony Stamper

IPC分类号： B01J19/12 ,  C25D5/02

CPC分类号： C23C8/02 ,  C23C8/04 ,  C23C8/10 ,  C23C8/24 ,  C25D11/00 ,  C25D11/02 ,  C25D11/026 ,  H01C7/006 ,  H01C17/26 ,  H01L21/263 ,  H01L27/0802 ,  H01L29/8605 ,  Y10S257/904 ,  Y10S257/914

摘要： A method for increasing an electrical resistance of a resistor, by nitridizing a fraction of a surface layer of the resistor with nitrogen particles. An embodiment comprises heating the fraction of the surface layer by a beam of radiation or particles, such that the resistor is within a chamber that includes the nitrogen-comprising molecules. An embodiment comprises using an anodization circuit to electrolytically generate nitrogen ions in an electrolytic solution in which the resistor is immersed, wherein the nitrogen particles include the electrolytically-generated nitrogen ions. An embodiment comprises immersing the resistor in a chemical solution which includes the nitrogen particles, wherein the nitrogen particles may include nitrogen-comprising liquid molecules, nitrogen ions, or a nitrogen-comprising gas dissolved in the chemical solution under pressurization. An embodiment comprises testing the resistor during a nitridizing step to determine whether the electrical resistance of the resistor is within a tolerance.

摘要翻译： 通过用氮颗粒氮化电阻表面层的一部分来提高电阻器的电阻的方法。 一个实施方案包括通过辐射束或颗粒束加热表面层的部分，使得电阻在包含含氮分子的室内。 一个实施例包括使用阳极氧化电路在其中浸入电阻器的电解液中电解产生氮离子，其中氮颗粒包括电解产生的氮离子。 一个实施方案包括将电阻器浸入包括氮颗粒的化学溶液中，其中氮颗粒可以包括在加压下溶解在化学溶液中的含氮液体分子，氮离子或含氮气体。 一个实施例包括在氮化步骤期间测试电阻器以确定电阻器的电阻是否在公差范围内。

公开(公告)号：US20080036092A1

公开(公告)日：2008-02-14

申请号：US11873300

申请日：2007-10-16

申请人： Jeffrey Gambino ,  Anthony Stamper

发明人： Jeffrey Gambino ,  Anthony Stamper

IPC分类号： H01L23/48

CPC分类号： H01L21/02167 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/312 ,  H01L21/3121 ,  H01L21/3122 ,  H01L21/3148 ,  H01L21/31612 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The present invention provides a method of forming a rigid interconnect structure, and the device therefrom, including the steps of providing a lower metal wiring layer having first metal lines positioned within a lower low-k dielectric; depositing an upper low-k dielectric atop the lower metal wiring layer; etching at least one portion of the upper low-k dielectric to provide at least one via to the first metal lines; forming rigid dielectric sidewall spacers in at least one via of the upper low-k dielectric; and forming second metal lines in at least one portion of the upper low-k dielectric. The rigid dielectric sidewall spacers may comprise of SiCH, SiC, SiNH, SiN, or SiO2. Alternatively, the via region of the interconnect structure may be strengthened with a mechanically rigid dielectric comprising SiO2, SiCOH, or doped silicate glass.

摘要翻译： 本发明提供一种形成刚性互连结构及其装置的方法，包括以下步骤：提供具有位于下部低k电介质内的第一金属线的下金属布线层; 在下部金属布线层的顶部沉积上部低k电介质; 蚀刻上部低k电介质的至少一部分以向第一金属线提供至少一个通孔; 在所述上部低k电介质的至少一个通路中形成刚性电介质侧壁间隔物; 以及在所述上部低k电介质的至少一部分中形成第二金属线。 刚性电介质侧壁间隔物可以包括SiCH，SiC，SiNH，SiN或SiO 2。 或者，可以用包含SiO 2，SiCOH或掺杂硅酸盐玻璃的机械刚性电介质来加强互连结构的通孔区域。

公开(公告)号：US20070252282A1

公开(公告)日：2007-11-01

申请号：US11772899

申请日：2007-07-03

申请人： Brent Anderson ,  Andres Bryant ,  Jeffrey Gambino ,  Anthony Stamper

发明人： Brent Anderson ,  Andres Bryant ,  Jeffrey Gambino ,  Anthony Stamper

IPC分类号： H01L23/52

CPC分类号： H01L21/7682 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Air-gap insulated interconnection structures and methods of fabricating the structures, the methods including: forming a dielectric layer on a substrate; forming a capping layer on a top surface of the dielectric layer; forming a trench through the capping layer, the trench extending toward said substrate and into but not through, the dielectric layer; forming a sacrificial layer on opposing sidewalls of the trench; filling the trench with a electrical conductor; and removing a portion of the sacrificial layer from between the electrical conductor and the dielectric layer to form air-gaps.

摘要翻译： 气隙绝缘互连结构及其制造方法，包括：在基板上形成电介质层; 在所述电介质层的顶表面上形成覆盖层; 通过所述覆盖层形成沟槽，所述沟槽朝向所述衬底延伸并且穿过所述电介质层; 在沟槽的相对侧壁上形成牺牲层; 用电导体填充沟槽; 以及从所述电导体和所述电介质层之间移除所述牺牲层的一部分以形成气隙。