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237 条记录 (耗时 0.048 秒)

    Reconfigurable I/O DRAM
    41.
    发明授权
    Reconfigurable I/O DRAM 失效
    可重配置I / O DRAM

    公开(公告)号：US6070262A

    公开(公告)日：2000-05-30

    申请号：US833367

    申请日：1997-04-04

    申请人： Mark W. Kellogg ,  Timothy J. Dell ,  Erik L. Hedberg ,  Claude L. Bertin

    发明人： Mark W. Kellogg ,  Timothy J. Dell ,  Erik L. Hedberg ,  Claude L. Bertin

    IPC分类号： G06F11/10 ,  G06F12/00 ,  G11C7/10 ,  G11C29/00

    CPC分类号： G11C7/1057 ,  G06F11/1044 ,  G11C7/1006 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1084

    摘要： A Dynamic Random Access Memory (DRAM) configurable by eight (.times.8) or by nine (.times.9). The DRAM has nine Data Input/Outputs (I/Os). The memory array is divided into two or more sub-arrays, with sub-array cells arranged in addressable rows and columns. When the DRAM is configured .times.8, one I/O is held in its high impedance state; one ninth of the DRAM's data path (between the array and the ninth I/O) is ignored; and, the entire array address space is available for data storage through eight I/Os. When the DRAM is configured .times.9, all nine I/Os are active; the DRAM I/O path is reconfigured with part of the array providing the ninth bit through the ninth I/O; and the array address space reduced by one-eighth. All nine bits may be from a common sub-array. Alternatively, sub-arrays may be paired so that when the DRAM is configured .times.9, eight bits are accessed in seven-eighths of one sub-array, with the ninth bit being accessed in one eighth of the other sub-array of the pair.

    摘要翻译： 动态随机存取存储器（DRAM）可由八（x8）或九（x9）配置。 DRAM具有9个数据输入/输出（I / O）。 存储器阵列被分成两个或更多个子阵列，子阵列单元被布置成可寻址的行和列。 当DRAM被配置为x8时，一个I / O保持在其高阻抗状态; DRAM的数据路径（阵列和第九个I / O之间）的九分之一被忽略; 并且整个阵列地址空间可用于通过八个I / O进行数据存储。 当DRAM配置为x9时，所有9个I / O都有效; DRAM I / O路径被配置为通过第九个I / O提供第九位的阵列的一部分; 并且阵列地址空间减少了八分之一。 所有9位可能来自公共子阵列。 或者，子阵列可以配对，使得当DRAM被配置为x9时，在一个子阵列的七分之八中访问八个比特，其中第九比特在该对的另一个子阵列的八分之一中被访问。

    Method for making sub-lithographic images by etching the intersection of two spacers
    42.
    发明授权
    Method for making sub-lithographic images by etching the intersection of two spacers 失效
    通过蚀刻两个间隔物进行亚光刻图像的方法

    公开(公告)号：US5714039A

    公开(公告)日：1998-02-03

    申请号：US539244

    申请日：1995-10-04

    申请人： Kenneth E. Beilstein, Jr. ,  Claude L. Bertin ,  James M. Leas ,  Jack A. Mandelman

    发明人： Kenneth E. Beilstein, Jr. ,  Claude L. Bertin ,  James M. Leas ,  Jack A. Mandelman

    IPC分类号： H01L21/306 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/46 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/3105

    CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144

    摘要： A method of forming a sub-lithographic image formed by the intersection of two spacers. A substrate with a first pattern of selectively etchable material with sidewalls that are substantially vertical is provided. A first sidewall spacer is formed of a material that is selectively etchable relative to the first pattern material. A second pattern of a selectively etchable material is formed with the second pattern intersecting the first pattern. The sidewalls of the second pattern are substantially vertical as well. A second sidewall spacer is formed of a material that is selectively etchable relative to the second pattern material. The second pattern material is etched to leave the second sidewall spacer. Alternatively, the first and/or second pattern materials may be totally removed, left in place, or planarized.

    摘要翻译： 一种形成由两个间隔物相交形成的亚光刻图像的方法。 提供具有基本上垂直的侧壁的具有可选择性蚀刻材料的第一图案的衬底。 第一侧壁间隔物由相对于第一图案材料可选择性蚀刻的材料形成。 形成与第一图案相交的第二图案的可选择性蚀刻材料的第二图案。 第二图案的侧壁也是基本垂直的。 第二侧壁间隔件由相对于第二图案材料可选择地蚀刻的材料形成。 蚀刻第二图案材料以离开第二侧壁间隔物。 或者，第一和/或第二图案材料可以被完全去除，留在原位或平坦化。

    Monolithic electronic modules--fabrication and structures
    43.
    发明授权
    Monolithic electronic modules--fabrication and structures 失效
    单片电子模块 - 制造和结构

    公开(公告)号：US5614277A

    公开(公告)日：1997-03-25

    申请号：US429992

    申请日：1995-04-27

    申请人： Kenneth E. Beilstein, Jr. ,  Claude L. Bertin ,  Wayne J. Howell

    发明人： Kenneth E. Beilstein, Jr. ,  Claude L. Bertin ,  Wayne J. Howell

    IPC分类号： H01L21/28 ,  H01L21/98 ,  H01L25/065 ,  H05K3/34

    CPC分类号： H01L25/50 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551 ,  Y10S269/903 ,  Y10S269/909 ,  Y10S428/914 ,  Y10T29/49124 ,  Y10T29/49144 ,  Y10T428/14 ,  Y10T428/1438 ,  Y10T428/1481 ,  Y10T428/24942

    摘要： This invention comprises various high production methods for simultaneously forming surface metallizations on a plurality of monolithic electronic modules. Each monolithic electronic module may comprise a single semiconductor chip or multiple semiconductor chips. The methods can employ a workpiece which automatically discontinues side surface metallization between different electronic modules in the stack. Multiple workpieces are interleaved within the stack between the electronic modules. Each workpiece may include a transfer layer(s) for permanent bonding to an end surface of an adjacent electronic module in the stack. This transfer layer may comprise an insulation layer, a metallization layer, an active circuit layer, or any combination thereof. End surface metallization can thus be provided contemporaneous with side surface metallization of multiple electronic modules.

    摘要翻译： 本发明包括用于在多个单片电子模块上同时形成表面金属化的各种高生产方法。 每个单片电子模块可以包括单个半导体芯片或多个半导体芯片。 该方法可以采用自动中断堆叠中不同电子模块之间的侧面金属化的工件。 多个工件在电子模块之间的堆叠内交错。 每个工件可以包括用于永久地结合到堆叠中的相邻电子模块的端面的转移层。 该转移层可以包括绝缘层，金属化层，有源电路层或其任何组合。 因此，可以同时提供多个电子模块的侧表面金属化的端面金属化。

    Resistive gate field effect transistor logic family
    47.
    发明授权
    Resistive gate field effect transistor logic family 失效
    电阻栅场效应晶体管逻辑系列

    公开(公告)号：US4602170A

    公开(公告)日：1986-07-22

    申请号：US530450

    申请日：1983-09-08

    申请人： Claude L. Bertin

    发明人： Claude L. Bertin

    IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/43 ,  H01L29/78 ,  H03K19/0944 ,  H03K19/094 ,  H03K19/20

    CPC分类号： H01L29/435 ,  H03K19/09441

    摘要： A family of digital logic circuits constructed with resistive gate field effect transistors is provided. The logic circuits are comprised of AND and OR circuits, each implemented with resistive gate devices. In constructing the AND circuit, the resistive gate lies along the length of the channel region between the source and drain of the device. Logic input signals are selectively applied along the length of the channel region to the resistive gate. The device will conduct between source and drain only if all points along the channel are above the local threshold voltage of the channel region which will occur when appropriate logic signals are applied simultaneously to all logic input terminals. A logic OR device is realized when the resistive gate is formed transverse to the channel such that each input to the gate controls a portion of the channel between the source and drain. NAND and NOR circuits are provided using the resistive gate logic device in an inverter circuit.

    摘要翻译： 提供了由电阻栅场效应晶体管构成的数字逻辑电路系列。 逻辑电路由AND和OR电路组成，每个电路都使用电阻栅极器件实现。 在构建AND电路时，电阻栅极沿着器件的源极和漏极之间的沟道区域的长度。 选择性地将逻辑输入信号沿通道区域的长度施加到电阻门。 只有沿着通道的所有点都高于通道区域的局部阈值电压，器件才会在源极和漏极之间导通，当适当的逻辑信号同时施加到所有逻辑输入端子时，该通道区域将发生。 当电阻栅极横穿于通道形成时，实现逻辑或器件，使得到栅极的每个输入控制源极和漏极之间的沟道的一部分。 在逆变器电路中使用电阻门逻辑器件提供NAND和NOR电路。

    Over voltage protective device and circuits for insulated gate transistors
    48.
    发明授权
    Over voltage protective device and circuits for insulated gate transistors 失效
    绝缘栅极晶体管的过电压保护器件和电路

    公开(公告)号：US4139935A

    公开(公告)日：1979-02-20

    申请号：US782574

    申请日：1977-03-29

    申请人： Claude L. Bertin ,  Francisco H. De La Moneda

    发明人： Claude L. Bertin ,  Francisco H. De La Moneda

    IPC分类号： H03F1/52 ,  H01L21/265 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L29/06 ,  H01L29/78 ,  H02H7/20 ,  H03F1/42 ,  H03K17/0812 ,  H01L21/26

    CPC分类号： H01L27/0251 ,  H01L21/2652 ,  H01L29/0688 ,  H03K17/08122

    摘要： Protective devices and circuits for insulated gate transistors are improved by another p/n junction diode or MOS diode preventing breakdown of the thin oxide of the protective device. The breakdown voltage of the protective device or p/n diode may be tailored to a preselected voltage by altering its metallurgical junction by ion implantation or other techniques. Tailoring permits the breakdown voltage of the protective device to be independent of process and circuit specification of a protected or internal circuit. A plurality of parallel circuits connected as a protective device limits or controls secondary breakdown of the protective device.

    摘要翻译： 用于绝缘栅极晶体管的保护器件和电路由另一个p / n结二极管或MOS二极管改善，以防止保护器件的薄氧化物破坏。 保护装置或p / n二极管的击穿电压可以通过改变其冶金接合通过离子注入或其它技术来调整为预选电压。 裁缝允许保护装置的击穿电压与受保护或内部电路的工艺和电路规格无关。 作为保护装置连接的多个并联电路限制或控制保护装置的二次击穿。