公开(公告)号：US09595493B2

公开(公告)日：2017-03-14

申请号：US14822597

申请日：2015-08-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhiguo Sun ,  Qiang Fang ,  Huang Liu ,  Haigou Huang ,  Jiehui Shu ,  Jin Ping Liu

IPC: H01L21/76 ,  H01L23/528 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L21/321

CPC classification number: H01L23/528 ,  H01L21/3065 ,  H01L21/321 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76853 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53204 ,  H01L23/53238 ,  H01L23/53266

Abstract: Reducing liner corrosion during metallization of semiconductor devices at BEOL includes providing a starting metallization structure, the structure including a bottom layer of dielectric material with a via therein, a liner lining the via and extending over upper edges thereof, the lined via over filled with a conductive material, recessing the conductive material down to the liner, further selectively recessing the conductive material below the upper edges of the via without damaging the liner, and forming a cap of the liner material on the conductive material.

Abstract translation: 在BEOL的半导体器件的金属化期间减少衬里腐蚀包括提供起始金属化结构，该结构包括介电材料的底层，其中具有通孔，衬套衬套通孔并在其上边缘延伸的衬里，衬里通孔填充有 导电材料将导电材料向下凹入衬垫，进一步选择性地使导电材料在通孔的上边缘下方凹陷，而不损坏衬垫，并且在导电材料上形成衬垫材料的帽。

公开(公告)号：US09230822B1

公开(公告)日：2016-01-05

申请号：US14306920

申请日：2014-06-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Haigou Huang ,  Jin Ping Liu ,  Huang Liu

IPC: H01L21/3105 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/31055 ,  H01L21/02318 ,  H01L21/02326 ,  H01L21/0234 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/823821 ,  H01L21/823842

Abstract: A semiconductor structure with mixed n-type and p-type non-planar transistors includes a residual overlapping mask bump on one or more of the dummy gates. A dielectric layer is created over the structure having a top surface above the residual bump, for example, using a blanket deposition and chemical-mechanical underpolish (i.e., stopping before exposing the gate cap). The residual bump is then transformed into a same material as the dielectric, either in its entirety and then removing the combined dielectric, or by removing the dielectric first and partly removing the residual bump, the remainder of which is then transformed and the dielectric removed. In either case, the structure is planarized for further processing.

Abstract translation: 具有混合n型和p型非平面晶体管的半导体结构包括在一个或多个虚拟栅极上的残留重叠掩模凸块。 例如，使用覆盖沉积和化学机械的低估（即，在暴露栅极盖之前停止），在该结构上方形成介电层，该顶表面具有顶部表面。 然后将剩余的凸块转变成与电介质完全相同的材料，然后去除组合的电介质，或者通过首先去除电介质并部分去除残余凸块，然后将其余部分转化并除去电介质。 在任一种情况下，将结构平坦化用于进一步处理。

公开(公告)号：US09123773B1

公开(公告)日：2015-09-01

申请号：US14461015

申请日：2014-08-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： HongLiang Shen ,  Fangyu Wu ,  Haigou Huang ,  Xusheng Wu ,  Changyong Xiao ,  Wanxum He

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/306 ,  H01L21/308 ,  H01L21/02 ,  H01L21/3065

CPC classification number: H01L21/76224 ,  H01L21/3086 ,  H01L21/76232 ,  H01L29/66795

Abstract: Methods of forming a T-shaped SBD using a single-mask process flow are disclosed. Embodiments include providing a substrate having STI regions; forming a hard mask layer over the substrate and the STI regions, the hard mask having an opening laterally separated from the STI regions; forming a recess in the substrate through the opening, the recess having a first width; forming spacers on sidewalls of the recess, with a gap therebetween; forming a trench in the substrate through the gap, the trench having a second width less than the first; removing the spacers; removing the hard mask layer; filling the trench and the recess with an oxide layer, forming a T-shaped STI region; forming another hard mask layer on a portion of the T-shaped STI region; and revealing a Fin by removing portions of the STI regions and the T-shaped STI region.

Abstract translation: 公开了使用单掩模工艺流程形成T形SBD的方法。 实施例包括提供具有STI区域的基板; 在所述基板和所述STI区域上形成硬掩模层，所述硬掩模具有与所述STI区域横向分离的开口; 通过所述开口在所述基板中形成凹部，所述凹部具有第一宽度; 在凹槽的侧壁上形成间隔物，其间具有间隙; 通过所述间隙在所述衬底中形成沟槽，所述沟槽具有小于所述第一宽度的第二宽度; 去除垫片; 去除硬掩模层; 用氧化物层填充沟槽和凹部，形成T形STI区域; 在T形STI区域的一部分上形成另一个硬掩模层; 并且通过去除STI区域和T形STI区域的部分来显露Fin。

公开(公告)号：US20140227858A1

公开(公告)日：2014-08-14

申请号：US13765723

申请日：2013-02-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hongliang Shen ,  Kyutae Na ,  Sandeep Gaan ,  Hsin-Neng Tai ,  Weihua Tong ,  Sang Cheol Han ,  Tae Hoon Kim ,  Ja Hyung Han ,  Haigou Huang ,  Changyong Xiao ,  Huang Liu ,  Seung Yeon Kim

IPC: H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/02123 ,  H01L21/76224 ,  H01L21/76229 ,  H01L27/0886

Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

Abstract translation: 本发明的方面通常涉及用于形成半导体器件的方法，例如在TSV和晶体管之间具有“缓冲区”或间隙层的TSV器件。 间隙层通常填充有低应力薄膜填充材料，其控制器件上的应力和裂纹形成。 此外，间隙层确保TSV和晶体管之间的一定空间距离，以减少温度偏移的不利影响。

公开(公告)号：US20200020531A1

公开(公告)日：2020-01-16

申请号：US16033714

申请日：2018-07-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yuping Ren ,  Guoxiang Ning ,  Haigou Huang ,  Sunil K. Singh

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768

Abstract: Methods of fabricating an interconnect structure. A hardmask is deposited over a dielectric layer, and a block mask is formed that is arranged over an area on the hardmask. After forming the block mask, a first mandrel and a second mandrel are formed on the hardmask. The first mandrel is laterally spaced from the second mandrel, and the area on the hardmask is arranged between the first mandrel and the second mandrel. The block mask may be used to provide a non-mandrel cut separating the tips of interconnects subsequently formed in the dielectric layer.

公开(公告)号：US20190326416A1

公开(公告)日：2019-10-24

申请号：US15956306

申请日：2018-04-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haigou Huang ,  Jiehui Shu ,  Chih-Chiang Chang ,  Xingzhao Shi ,  Jinsheng Gao ,  Huy Cao

IPC: H01L29/66 ,  H01L29/78

Abstract: Structures for a field-effect transistor and methods of forming a structure for field-effect transistor. A gate electrode is arranged in a lower portion of a trench in an interlayer dielectric layer, and a liner is formed inside an upper portion of the trench and over a top surface of the interlayer dielectric layer. A dielectric material is deposited in in the upper portion of the trench and over the liner on the top surface of the interlayer dielectric layer. The dielectric material is polished with a polishing process to remove the dielectric material from the liner on the top surface of the interlayer dielectric layer and to form a cap comprised of the dielectric material in the upper portion of the trench. The liner on the interlayer dielectric layer operates as a polish stop during the polishing process.

公开(公告)号：US10453754B1

公开(公告)日：2019-10-22

申请号：US16021660

申请日：2018-06-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jianwei Peng ,  Haigou Huang ,  Qun Gao ,  Xin Wang

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/324 ,  H01L21/02 ,  H01L21/225

Abstract: The present disclosure is directed to various methods of diffusing contact extension dopants in a transistor device and the resulting devices. One illustrative method includes forming a first contact opening between two adjacent gate structures formed above a first fin, the first contact opening exposing a first region of the first fin, forming a first contact recess in the first region, forming a first doped liner in the first contact recess, performing an anneal process to diffuse dopants from the first doped liner into the first fin to form a first doped contact extension region in the first fin, and performing a first epitaxial growth process to form a first source/drain region in the first contact recess.

公开(公告)号：US10418455B2

公开(公告)日：2019-09-17

申请号：US15716287

申请日：2017-09-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Daniel Jaeger ,  Haigou Huang ,  Veeraraghavan Basker ,  Christopher Nassar ,  Jinsheng Gao ,  Michael Aquilino

IPC: H01L21/02 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/225 ,  H01L21/321 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/417 ,  H01L27/092

Abstract: At least one method, apparatus and system disclosed herein involves forming trench in a gate region, wherein the trench having an oxide layer to a height to reduce or prevent process residue. A plurality of fins are formed on a semiconductor substrate. Over a first portion of the fins, an epitaxial (EPI) feature at a top portion of each fin of the first portion. Over a second portion of the fins, a gate region is formed. In a portion of the gate region, a trench is formed. A first oxide layer at a bottom region of the trench is formed. Prior to performing an amorphous-silicon (a-Si) deposition, a flowable oxide material is deposited into the trench for forming a second oxide layer. The second oxide layer comprises the flowable oxide and the first oxide layer. The second oxide layer has a first height.

公开(公告)号：US10388562B2

公开(公告)日：2019-08-20

申请号：US15678229

申请日：2017-08-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou Huang ,  Daniel Jaeger ,  Xusheng Wu ,  Jinsheng Gao

IPC: H01L21/336 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/02

Abstract: A composite etch stop layer includes an oxide layer formed over a sacrificial gate structure and a nitride layer formed over the oxide layer. The oxide layer is disposed over only lower portions of the sacrificial gate structure while the nitride layer envelops the oxide layer and is disposed directly over a top surface of the sacrificial gate structure. Sensitivity of the nitride layer to oxidation, such as during the formation of an interlayer dielectric over the composite etch stop layer, is decreased by eliminating the oxide layer from upper portions of the sacrificial gate layer.

公开(公告)号：US10269654B1

公开(公告)日：2019-04-23

申请号：US15890246

申请日：2018-02-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinsheng Gao ,  Daniel Jaeger ,  Michael Aquilino ,  Patrick Carpenter ,  Jessica Dechene ,  Huy Cao ,  Mitchell Rutkowski ,  Haigou Huang

IPC: H01L21/00 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L27/092

Abstract: At least one method, apparatus and system disclosed herein involves forming trench silicide region contact. A plurality of fins are formed on a semiconductor substrate. An epitaxial (EPI) feature is formed at a top portion of each fin of the first portion over a first portion of the fins. A gate region is formed over a second portion of the fins. A replacement metal gate (RMG) process is performed in the gate region. A trench is formed in a portion of the gate region. A void is formed adjacent the a portion of the gate region. A first silicon feature is formed in the trench. A second silicon feature is formed in the void. A TS cut region is formed over the trench. The first silicon feature and the second silicon feature are removed. A metallization process is performed in the void to form a contact.