公开(公告)号：US20190318931A1

公开(公告)日：2019-10-17

申请号：US15950364

申请日：2018-04-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Xiaohan Wang ,  Qiang Fang ,  Zhiguo Sun ,  Jinping Liu ,  Hui Zang

IPC: H01L21/033 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

Abstract: Methods of self-aligned multiple patterning and structures formed by self-aligned multiple patterning. A mandrel line is patterned from a first mandrel layer disposed on a hardmask and a second mandrel layer disposed over the first mandrel layer. A first section of the second mandrel layer of the mandrel line is removed to expose a first section of the first mandrel layer. The first section of the first mandrel layer is masked, and the second sections of the second mandrel layer and the underlying second portions of the first mandrel layer are removed to expose first portions of the hardmask. The first portions of the hardmask are then removed with an etching process to form a trench in the hardmask. A second portion of the hardmask is masked by the first portion of the first mandrel layer during the etching process to form a cut in the trench.

公开(公告)号：US20190273148A1

公开(公告)日：2019-09-05

申请号：US16415519

申请日：2019-05-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Zhao ,  Haiting Wang ,  David P. Brunco ,  Jiehui Shu ,  Shesh Mani Pandey ,  Jinping Liu ,  Scott Beasor

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/762 ,  H01L29/417

Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. An etch stop layer, a sacrificial layer, and a dielectric layer are arranged in a layer stack formed on a substrate. a plurality of openings are formed that extend through the layer stack to the substrate. A semiconductor material is epitaxially grown inside each of the plurality of openings from the substrate to form a plurality of fins embedded in the layer stack. The sacrificial layer is removed selective to the etch stop layer to reveal a section of each of the plurality of fins.

公开(公告)号：US10276374B2

公开(公告)日：2019-04-30

申请号：US15709730

申请日：2017-09-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Garo J. Derderian ,  Jinping Liu

IPC: H01L21/12 ,  H01L21/033 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/12

Abstract: The disclosure is directed to methods for forming a set of fins from a substrate. One embodiment of the disclosure includes: providing a stack over the substrate, the stack including a first oxide over the substrate, a first nitride over the pad oxide, a second oxide over the first nitride, and a first hardmask over the second oxide; patterning the first hard mask to form a first set of hardmask fins over the second oxide; oxidizing the first set of hardmask fins to convert the first set of hardmask fins into a set of oxide fins; using the set of oxide fins as a mask, etching the second oxide and the first nitride to expose portions of the first oxide thereunder such that remaining portions of the second oxide and the first nitride remain disposed beneath the set of oxide fins thereby defining a set of mask stacks; and using the set of mask stacks as a mask, etching the exposed portions of the first oxide and the substrate thereby forming the set of fins from the substrate.

公开(公告)号：US20190088478A1

公开(公告)日：2019-03-21

申请号：US15709730

申请日：2017-09-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Garo J. Derderian ,  Jinping Liu

IPC: H01L21/033 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/092 ,  H01L27/12 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/66

Abstract: The disclosure is directed to methods for forming a set of fins from a substrate. One embodiment of the disclosure includes: providing a stack over the substrate, the stack including a first oxide over the substrate, a first nitride over the pad oxide, a second oxide over the first nitride, and a first hardmask over the second oxide; patterning the first hard mask to form a first set of hardmask fins over the second oxide; oxidizing the first set of hardmask fins to convert the first set of hardmask fins into a set of oxide fins; using the set of oxide fins as a mask, etching the second oxide and the first nitride to expose portions of the first oxide thereunder such that remaining portions of the second oxide and the first nitride remain disposed beneath the set of oxide fins thereby defining a set of mask stacks; and using the set of mask stacks as a mask, etching the exposed portions of the first oxide and the substrate thereby forming the set of fins from the substrate.

公开(公告)号：US20190027556A1

公开(公告)日：2019-01-24

申请号：US15656574

申请日：2017-07-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Rishikesh Krishnan ,  Jinping Liu ,  Yiheng Xu ,  Joseph F. Shepard, JR.

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/02 ,  H01L21/3105

Abstract: A method of forming a shallow trench isolation (STI) for an integrated circuit (IC) structure to mitigate fin bending disclosed. The method may include forming a first insulator layer in a first portion of an opening in a substrate by a bottom-up atomic layer deposition (ALD) process; and forming a second insulator layer on the first insulator layer in a second portion of the opening. The opening may be position between a set of fins in the substrate. The method may further include forming an oxide liner in the opening before the forming the first insulator layer. The second insulator layer may be formed by deposition using a flowable chemical vapor deposition (FCVD) process, high aspect ratio process (HARP), high-density plasma chemical vapor deposition (HDP CVD) process, or any other conventional insulator material deposition process.

公开(公告)号：US20180248046A1

公开(公告)日：2018-08-30

申请号：US15445392

申请日：2017-02-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  John Zhang ,  Haigou Huang ,  Jiehui Shu

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L29/423

CPC classification number: H01L29/78618 ,  H01L21/02532 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78684

Abstract: A plurality of vertically oriented channel semiconductor structures is formed above a substrate. A bottom source/drain (S/D) region is formed proximate a lower portion of the vertically oriented channel semiconductor structure. A first dielectric layer is formed above the vertically oriented channel semiconductor structure. A thickness of the first dielectric layer is reduced to expose an upper portion of the vertically oriented channel semiconductor structure. A first semiconductor material region is formed on the exposed upper portion. The thickness of the first dielectric layer is further reduced to expose a channel portion of the vertically oriented channel semiconductor structure and to define a bottom spacer adjacent the bottom S/D region. A gate structure is formed around the channel region of the vertically oriented channel semiconductor structure. A second semiconductor material region is formed on the upper portion to define an upper S/D region after forming the gate structure.

公开(公告)号：US10002793B1

公开(公告)日：2018-06-19

申请号：US15464591

申请日：2017-03-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  David P. Brunco ,  Jinping Liu ,  Baofu Zhu ,  Shesh Mani Pandey

IPC: H01L21/76 ,  H01L21/8234 ,  H01L21/761 ,  H01L21/225

CPC classification number: H01L21/2254 ,  H01L21/823431 ,  H01L21/823493 ,  H01L21/823821 ,  H01L21/823892

Abstract: A gap fill method for sub-fin doping includes forming semiconductor fin arrays over a semiconductor substrate, forming a first dopant source layer over a first fin array and filling intra fin gaps within the first array, and forming a second dopant source layer over a second fin array and filling intra fin gaps within the second array. The first and second dopant source layers are recessed to expose a channel region of the fins. Thereafter, an annealing step is used to drive dopants from the dopant source layers locally into sub-fin regions of the fins below the channel regions.

公开(公告)号：US09984933B1

公开(公告)日：2018-05-29

申请号：US15723416

申请日：2017-10-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yiheng Xu ,  Haiting Wang ,  Wei Zhao ,  Todd B. Abrams ,  Jiehui Shu ,  Jinping Liu ,  Scott Beasor

IPC: H01L21/311 ,  H01L21/8234 ,  H01L21/306 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L21/823431 ,  H01L21/28123 ,  H01L21/30625 ,  H01L21/823481 ,  H01L29/785

Abstract: A hardmask is patterned on a first material to leave hardmask elements. The first material is patterned into fins through the hardmask. A layer of silicon is formed on the hardmask elements and the fins in processing that forms the layer of silicon thicker on the hardmask elements relative to the fins. An isolation material is formed on the layer of silicon to leave the isolation material filling spaces between the fins. The isolation material and the layer of silicon are annealed to consume relatively thinner portions of the layer of silicon and leave the layer of silicon on the hardmask elements as silicon elements. A chemical mechanical polishing (CMP) is performed on the isolation material to make the isolation material planar with the silicon elements. A first etching agent removes the silicon elements on the hardmask elements, and a second chemical agent removes the hardmask elements.

公开(公告)号：US09761452B1

公开(公告)日：2017-09-12

申请号：US15205528

申请日：2016-07-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Daniel Jaeger ,  Garo Jacques Derderian ,  Haifeng Sheng ,  Jinping Liu

IPC: H01L21/311 ,  H01L21/033 ,  H01L27/11

CPC classification number: H01L27/1116 ,  H01L21/3086 ,  H01L27/1104 ,  H01L28/00

Abstract: Devices and methods of fabricating integrated circuit devices with reduced cell height are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate including a logic area and an SRAM area, a fin material layer, and a hardmask layer; depositing a mandrel over the logic area; depositing a sacrificial spacer layer; etching the sacrificial spacer layer to define a sacrificial set of vertical spacers; etching the hardmask layer; leaving a set of vertical hardmask spacers; depositing a first spacer layer; etching the first spacer layer to define a first set of vertical spacers over the logic area; depositing an SOH layer; etching an opening in the SOH layer over the SRAM area; depositing a second spacer layer; and etching the second spacer layer to define a second set of spacers over the SRAM area.

公开(公告)号：US09595493B2

公开(公告)日：2017-03-14

申请号：US14822597

申请日：2015-08-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhiguo Sun ,  Qiang Fang ,  Huang Liu ,  Haigou Huang ,  Jiehui Shu ,  Jin Ping Liu

IPC: H01L21/76 ,  H01L23/528 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L21/321

CPC classification number: H01L23/528 ,  H01L21/3065 ,  H01L21/321 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76853 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53204 ,  H01L23/53238 ,  H01L23/53266

Abstract: Reducing liner corrosion during metallization of semiconductor devices at BEOL includes providing a starting metallization structure, the structure including a bottom layer of dielectric material with a via therein, a liner lining the via and extending over upper edges thereof, the lined via over filled with a conductive material, recessing the conductive material down to the liner, further selectively recessing the conductive material below the upper edges of the via without damaging the liner, and forming a cap of the liner material on the conductive material.

Abstract translation: 在BEOL的半导体器件的金属化期间减少衬里腐蚀包括提供起始金属化结构，该结构包括介电材料的底层，其中具有通孔，衬套衬套通孔并在其上边缘延伸的衬里，衬里通孔填充有 导电材料将导电材料向下凹入衬垫，进一步选择性地使导电材料在通孔的上边缘下方凹陷，而不损坏衬垫，并且在导电材料上形成衬垫材料的帽。