公开(公告)号：US09171804B2

公开(公告)日：2015-10-27

申请号：US13681079

申请日：2012-11-19

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Khalil Hosseini ,  Joachim Mahler ,  Edward Fuergut

IPC: H01L21/58 ,  H01L21/78 ,  H01L23/538 ,  H01L23/00 ,  H01L23/495 ,  H01L21/56

CPC classification number: H01L23/5384 ,  H01L21/561 ,  H01L21/563 ,  H01L21/78 ,  H01L23/49513 ,  H01L23/49562 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/32245 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2224/83203 ,  H01L2224/83207 ,  H01L2224/83439 ,  H01L2224/83455 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15747 ,  H01L2924/00

Abstract: A carrier and a semiconductor chip are provided. A connection layer is applied to a first main face of the semiconductor chip. The connection layer includes a plurality of depressions. A filler is applied to the connection layer or to the carrier. The semiconductor chip is attached to the carrier so that the connection layer is disposed between the semiconductor chip and the carrier. The semiconductor chip is affixed to the carrier.

Abstract translation: 提供载体和半导体芯片。 连接层被施加到半导体芯片的第一主面。 连接层包括多个凹陷。 将填料施加到连接层或载体上。 将半导体芯片附着到载体上，使得连接层设置在半导体芯片和载体之间。 半导体芯片固定在载体上。

公开(公告)号：US09082767B2

公开(公告)日：2015-07-14

申请号：US14151917

申请日：2014-01-10

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Edward Fuergut ,  Khalil Hosseini ,  Georg Meyer-Berg

IPC: H01L21/56 ,  H01L23/498 ,  H01L23/48 ,  H01L23/28 ,  H01L21/58 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/49811 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/19 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/014 ,  H01L2924/00

Abstract: A embedded integrated circuit package is provided, the embedded integrated circuit package including: at least one chip arranged over a chip carrier, the at least one chip including a plurality of chip contact pads; encapsulation material formed over the chip carrier and at least partially surrounding the at least one chip; a plurality of electrical interconnects formed through the encapsulation material, wherein each electrical interconnect is electrically connected to a chip contact pad; and a structure formed between the electrical interconnects of the embedded integrated circuit package, wherein the structure increases the creepage resistance between the electrical interconnects.

Abstract translation: 提供一种嵌入式集成电路封装，所述嵌入式集成电路封装包括：至少一个布置在芯片载体上的芯片，所述至少一个芯片包括多个芯片接触焊盘; 形成在所述芯片载体上并且至少部分地围绕所述至少一个芯片的封装材料; 通过所述封装材料形成的多个电互连，其中每个电互连电连接到芯片接触焊盘; 以及形成在嵌入式集成电路封装的电互连之间的结构，其中该结构增加了电互连之间的耐爬电阻性。

公开(公告)号：US20150028448A1

公开(公告)日：2015-01-29

申请号：US13951556

申请日：2013-07-26

Applicant: Infineon Technologies AG

Inventor： Khalil Hosseini ,  Joachim Mahler ,  Georg Meyer-Berg

IPC: H01L25/065 ,  H01L23/12 ,  H01L49/02 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/12 ,  H01L23/492 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/85 ,  H01L25/072 ,  H01L25/16 ,  H01L25/18 ,  H01L28/00 ,  H01L2224/04105 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/16265 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/24226 ,  H01L2224/24246 ,  H01L2224/24265 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/85 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/013 ,  H01L2924/0105 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A chip package includes an electrically conducting chip carrier and at least one first semiconductor chip attached to the electrically conducting chip carrier. The chip package further includes a passive component. The electrically conducting chip carrier, the at least one first semiconductor chip, and the passive component are embedded in an insulating laminate structure.

Abstract translation: 芯片封装包括导电芯片载体和连接到导电芯片载体的至少一个第一半导体芯片。 芯片封装进一步包括无源元件。 导电芯片载体，至少一个第一半导体芯片和无源部件被嵌入绝缘层压结构中。

公开(公告)号：US20140145333A1

公开(公告)日：2014-05-29

申请号：US13689511

申请日：2012-11-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Georg Meyer-Berg ,  Reinhard Pufall

IPC: H01L23/532 ,  G01R31/26 ,  H01L21/768

CPC classification number: H01L22/32 ,  G01R31/26 ,  G01R31/28 ,  G01R31/2853 ,  G01R31/2884 ,  H01L21/7685 ,  H01L21/76868 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/53204 ,  H01L23/58 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/05556 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00

Abstract: Device comprising a ductile layer, a method for making a component comprising a ductile layer and a method for testing a component are disclosed. An embodiment includes an electronic device including a first conductive layer, a ductile layer and a brittle layer between the first conductive layer and the ductile layer.

Abstract translation: 公开了包括延展层的装置，用于制造包括延展层的部件的方法和用于测试部件的方法。 实施例包括在第一导电层和延性层之间包括第一导电层，延性层和脆性层的电子器件。

公开(公告)号：US11322451B2

公开(公告)日：2022-05-03

申请号：US16249172

申请日：2019-01-16

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Juergen Hoegerl ,  Gottfried Beer ,  Magdalena Hoier ,  Georg Meyer-Berg

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/373 ,  H01L23/498

Abstract: A power semiconductor module includes a power semiconductor die attached to the first metallized side, a passive component attached to the first metallized side, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component.

公开(公告)号：US10854547B2

公开(公告)日：2020-12-01

申请号：US16279370

申请日：2019-02-19

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Georg Meyer-Berg ,  Guenter Tutsch

IPC: H01L23/532 ,  H01L23/31 ,  H01L23/495 ,  H01L21/56 ,  H01L25/07 ,  H01L23/00

Abstract: A package and method of manufacturing a package is disclosed. In one example, the package includes an electronic chip and a dielectric structure comprising a highly filled cross-linked thermoplastic material.

公开(公告)号：US20190109112A1

公开(公告)日：2019-04-11

申请号：US15725796

申请日：2017-10-05

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Georg Meyer-Berg

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  C09J5/06

Abstract: A semiconductor package includes a semiconductor die, a substrate for supporting the semiconductor die, an encapsulant covering the semiconductor die and at least part of the substrate, and a die attach material attaching the semiconductor die to the substrate. The die attach material includes molecules having a first functional group with at least one free electron pair and a second functional group chemically reacted or reactable with the encapsulant in a way that promotes adhesion with the encapsulant. A corresponding method of manufacturing the semiconductor package is also described.

公开(公告)号：US10211158B2

公开(公告)日：2019-02-19

申请号：US14529371

申请日：2014-10-31

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Juergen Hoegerl ,  Gottfried Beer ,  Magdalena Hoier ,  Georg Meyer-Berg

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/498

Abstract: A power semiconductor module includes a direct copper bonded (DCB) substrate having a ceramic substrate, a first copper metallization bonded to a first main surface of the ceramic substrate and a second copper metallization bonded to a second main surface of the ceramic substrate opposite the first main surface. The power semiconductor module further includes a power semiconductor die attached the first copper metallization, a passive component attached the first copper metallization, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component. An integrated power module and a method of manufacturing the integrated power module are also provided.

公开(公告)号：US10056295B2

公开(公告)日：2018-08-21

申请号：US15002009

申请日：2016-01-20

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Claus von Waechter ,  Michael Bauer ,  Holger Doepke ,  Dominic Maier ,  Daniel Porwol ,  Tobias Schmidt

IPC: H01L21/78 ,  H01L21/683 ,  B32B37/26 ,  H01L21/56 ,  H01L23/00 ,  H05K3/00

CPC classification number: H01L21/78 ,  B32B37/26 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/562 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68381 ,  H05K3/007 ,  Y10S156/93 ,  Y10S156/941

Abstract: A method for handling a product substrate includes bonding a carrier to the product substrate. A layer of a permanent adhesive is applied onto a surface of the carrier. A structured intermediate layer is provided. The applied permanent adhesive bonds the carrier to the product substrate. The structured intermediate layer is arranged between the product substrate and the carrier. A surface of the structured intermediate layer and a surface of the permanent adhesive are in direct contact to a surface of the product substrate. The structured intermediate layer decreases a bonding strength between the product substrate and the carrier.

公开(公告)号：US09627305B2

公开(公告)日：2017-04-18

申请号：US13939248

申请日：2013-07-11

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Reinhard Pufall ,  Michael Goroll ,  Rainer Dudek

IPC: H01L23/498 ,  G06F17/50 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L23/04 ,  G06F17/5068 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49811 ,  H01L24/81 ,  H01L25/10 ,  H01L2224/01 ,  H01L2224/291 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/83447 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/35121 ,  H05K1/181 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A semiconductor package includes a support substrate having opposing first and second main surfaces and sides between the first and second main surfaces, a semiconductor die attached to one of the main surfaces of the support substrate, and an encapsulation material at least partly covering the support substrate and the semiconductor die. A protrusion extends outward from a side of the support substrate and terminates in the encapsulation material. The protrusion forms an interlocked connection with the encapsulation material. The interlocked connection increases the tensile strength of the interface between the encapsulation material and the side of the support substrate with the protrusion.