公开(公告)号：US20250015003A1

公开(公告)日：2025-01-09

申请号：US18887990

申请日：2024-09-17

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Rahul MANEPALLI ,  Gang DUAN

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer.

公开(公告)号：US20240321656A1

公开(公告)日：2024-09-26

申请号：US18126134

申请日：2023-03-24

Applicant: Intel Corporation

Inventor： Gang DUAN ,  Aaron GARELICK ,  Brandon C. MARIN ,  Srinivas V. PIETAMBARAM

IPC: H01L23/15 ,  H01L23/498

CPC classification number: H01L23/15 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838

Abstract: Embodiments disclosed herein include package substrates. In an embodiment, the package substrate comprises a core, where the core comprises glass, and an insert in the core. In an embodiment, the insert is a different material than the core. In an embodiment, a first layer is over the core and a second layer is under the core. In an embodiment, a notch is provided through the first layer, the core, and the second layer. In an embodiment, the notch passes through the insert in the core.

公开(公告)号：US20240312888A1

公开(公告)日：2024-09-19

申请号：US18121264

申请日：2023-03-14

Applicant: Intel Corporation

Inventor： Sashi S. KANDANUR ,  Srinivas V. PIETAMBARAM ,  Darko GRUJICIC ,  Brandon C. MARIN ,  Suddhasattwa NAD ,  Benjamin DUONG ,  Gang DUAN ,  Mohammad Mamunur RAHMAN ,  Numair AHMED

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/15

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49838

Abstract: Embodiments herein relate to systems, apparatuses, techniques and/or processes for creating a substrate out of a plurality of layers of glass, where the substrate includes one or more vias that extend through each of the plurality of layers of glass. In embodiments, a high aspect ratio via may be constructed through the substrate by electrically coupling the individual vias. Other embodiments may be described and/or claimed.

公开(公告)号：US20240222286A1

公开(公告)日：2024-07-04

申请号：US18091014

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Mohammad Mamunur RAHMAN ,  Brandon C. MARIN ,  Gang DUAN

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5389 ,  H01L23/5385 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/80 ,  H01L24/95 ,  H01L25/0655 ,  H01L25/50 ,  H01L23/481

Abstract: Embodiments disclosed herein include electronic packages and methods of forming electronic packages. In an embodiment, the electronic package comprises a die layer, with a first side and a second side opposite from the first side. In an embodiment, the die layer comprises a first die, and a second die. In an embodiment, a bridge is on the first side of the die layer, where the bridge communicatively couples the first die to the second die. In an embodiment, electrically conductive routing is on the second side of the die layer.

公开(公告)号：US20240203805A1

公开(公告)日：2024-06-20

申请号：US18084275

申请日：2022-12-19

Applicant: Intel Corporation

Inventor： Mohammad Mamunur RAHMAN ,  Brandon C. MARIN ,  Gang DUAN

IPC: H01L23/15 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/15 ,  H01L23/49816 ,  H01L23/5384 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  G06F12/0897

Abstract: Embodiments disclosed herein include electronic package packages. In an embodiment, the electronic package comprises a package substrate. In an embodiment, a first die is embedded in the package substrate, and a second die is over the package substrate. In an embodiment, the first die is entirely within a footprint of the second die.

公开(公告)号：US20240186280A1

公开(公告)日：2024-06-06

申请号：US18060596

申请日：2022-12-01

Applicant: Intel Corporation

Inventor： Minglu LIU ,  Andrey GUNAWAN ,  Gang DUAN ,  Edvin CETEGEN ,  Yuting WANG ,  Mine KAYA ,  Kartik SRINIVASAN ,  Mihir OKA ,  Anurag TRIPATHI

IPC: H01L23/00

CPC classification number: H01L24/75 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/7598 ,  H01L2224/75985 ,  H01L2224/81093 ,  H01L2224/81097 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/95093 ,  H01L2224/97 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2924/3841

Abstract: The present disclosure is directed to an apparatus having a bond head configured to heat and compress a semiconductor package assembly, and a bonding stage configured to hold the semiconductor package assembly, wherein the bonding stage comprises a ceramic material including silicon and either magnesium or indium.

公开(公告)号：US20240178151A1

公开(公告)日：2024-05-30

申请号：US18071901

申请日：2022-11-30

Applicant: Intel Corporation

Inventor： Minglu LIU ,  Alexander AGUINAGA ,  Gang DUAN ,  Jung Kyu HAN ,  Yosuke KANAOKA ,  Yi LI ,  Robin MCREE ,  Hong Seung YEON

IPC: H01L23/544 ,  H01L23/15 ,  H01L23/498

CPC classification number: H01L23/544 ,  H01L23/15 ,  H01L23/49816

Abstract: Embodiments disclosed herein include a package architecture. In an embodiment, the package architecture comprises a first substrate with a first fiducial mark on a surface of the first substrate. In an embodiment, the package architecture further comprises a second substrate over the first substrate, where the second substrate comprises glass and a second fiducial mark on the second substrate, and where a footprint of the second fiducial mark at least partially overlaps a footprint of the first fiducial mark.

公开(公告)号：US20240105571A1

公开(公告)日：2024-03-28

申请号：US17954288

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Haobo CHEN ,  Bai NIE ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Jeremy D. ECTON ,  Suddhasattwa NAD

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/49894 ,  H01L23/15

Abstract: Embodiments disclosed herein include glass cores and methods of forming glass cores. In an embodiment, a core for an electronic package comprises a substrate with a first surface and a second surface opposite from the first surface, where the substrate comprises glass, In an embodiment, a via opening is provided through the substrate, and a diffusion layer is along the first surface, the second surface, and the via opening.

公开(公告)号：US20240097079A1

公开(公告)日：2024-03-21

申请号：US17949857

申请日：2022-09-21

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Khaled AHMED ,  Srinivas V. PIETAMBARAM ,  Hiroki TANAKA ,  Paul WEST ,  Kristof DARMAWIKARTA ,  Gang DUAN ,  Jeremy D. ECTON ,  Suddhasattwa NAD

IPC: H01L33/48 ,  H01L25/075 ,  H01L33/00 ,  H01L33/32 ,  H01L33/62

CPC classification number: H01L33/486 ,  H01L25/0753 ,  H01L33/0075 ,  H01L33/32 ,  H01L33/62 ,  H01L2933/0066

Abstract: Integrated circuit (IC) packages are disclosed. In some embodiments, an IC package includes a glass substrate, a micro light emitting diode (LED), a semiconductor die, one or more through glass vias (TGVs) and a package substrate. The micro LED is positioned over the glass substrate. The TGVs are integrated into the glass substrate and connect the micro LED to the semiconductor die. The semiconductor die is connected to the package substrate to receive external signals when connected to a motherboard.

公开(公告)号：US20240087971A1

公开(公告)日：2024-03-14

申请号：US17943915

申请日：2022-09-13

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Gang DUAN ,  Srinivas V. PIETAMBARAM ,  Kristof DARMAWIKARTA ,  Jeremy D. ECTON ,  Suddhasattwa NAD ,  Hiroki TANAKA ,  Pooya TADAYON

IPC: H01L23/15 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/15 ,  H01L23/5381 ,  H01L23/5384 ,  H01L24/16 ,  H01L2224/16225

Abstract: Embodiments disclosed herein include interposers and methods of forming interposers. In an embodiment, an interposer comprises a substrate with a first surface and a second surface opposite from the first surface, where the substrate comprises glass. In an embodiment, the interposer further comprises a cavity into the first surface of the substrate, a via through the substrate below the cavity, a first pad in the cavity over the via, and a second pad on the second surface of the substrate under the via.