公开(公告)号：US20210343856A1

公开(公告)日：2021-11-04

申请号：US17336149

申请日：2021-06-01

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Sou-Chi Chang ,  Chia-Ching Lin ,  Jack Kavalieros ,  Uygar Avci ,  Ian Young

IPC: H01L29/51 ,  H01L29/15 ,  H01L29/221 ,  H01L29/94

Abstract: Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by providing tensile stress along a plane (e.g., x-axis) of a ferroelectric or anti-ferroelectric material of the ferroelectric/anti-ferroelectric based capacitor. Tensile stress is provided by a spacer comprising metal, semimetal, or oxide (e.g., metal or oxide of one or more of: Al, Ti, Hf, Si, Ir, or N). The tensile stress provides polar orthorhombic phase to the ferroelectric material and tetragonal phase to the anti-ferroelectric material. As such, memory window and reliability of the ferroelectric/anti-ferroelectric oxide thin film improves.

公开(公告)号：US20210305398A1

公开(公告)日：2021-09-30

申请号：US16833375

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Sou-Chi Chang ,  Chia-Ching Lin ,  Nazila Haratipour ,  Tanay Gosavi ,  I-Cheng Tung ,  Seung Hoon Sung ,  Ian Young ,  Jack Kavalieros ,  Uygar Avci ,  Ashish Verma Penumatcha

IPC: H01L29/51 ,  H01L29/92 ,  H01L29/24

Abstract: A capacitor device includes a first electrode having a first metal alloy or a metal oxide, a relaxor ferroelectric layer adjacent to the first electrode, where the ferroelectric layer includes oxygen and two or more of lead, barium, manganese, zirconium, titanium, iron, bismuth, strontium, neodymium, potassium, or niobium and a second electrode coupled with the relaxor ferroelectric layer, where the second electrode includes a second metal alloy or a second metal oxide.

公开(公告)号：US20200091308A1

公开(公告)日：2020-03-19

申请号：US16130903

申请日：2018-09-13

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Uygar Avci ,  Sou-Chi Chang ,  Ian Young

IPC: H01L29/51 ,  H01L29/78 ,  H01L27/11502 ,  H01L27/11585 ,  G11C11/22

Abstract: A capacitor is provided which comprises: a first structure comprising metal; a second structure comprising metal; and a third structure between the first and second structures, wherein the third structure comprises an improper ferroelectric material. In some embodiments, a field effect transistor (FET) is provided which comprises: a substrate; a source and drain adjacent to the substrate; and a gate stack between the source and drain, wherein the gate stack includes: a dielectric; a first structure comprising improper ferroelectric material, wherein the first structure is adjacent to the dielectric; and a second structure comprising metal, wherein the second structure is adjacent to the first structure.

公开(公告)号：US20190334026A1

公开(公告)日：2019-10-31

申请号：US15962634

申请日：2018-04-25

Applicant: INTEL CORPORATION

Inventor： Raseong Kim ,  Uygar Avci ,  Ian Young

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66

Abstract: An embodiment includes an apparatus comprising: a transistor including an epitaxial source, a channel, and an epitaxial drain; a fin that includes the channel, the channel including a long axis and a short axis; a source contact corresponding to the source; and a drain contact corresponding to the drain; wherein (a) an additional axis intersects each of the source contact, the source, the drain, and the drain contact, and (b) the additional axis is parallel to the long axis. Other embodiments are described herein.

公开(公告)号：US09741832B2

公开(公告)日：2017-08-22

申请号：US15122402

申请日：2014-03-28

Applicant: INTEL CORPORATION

Inventor： Uygar Avci ,  Dmitri Nikonov ,  Ian Young

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/10 ,  H01L29/08 ,  H01L29/24 ,  H01L29/786 ,  H01L49/00 ,  H01L29/423

CPC classification number: H01L29/66977 ,  H01L25/16 ,  H01L29/0847 ,  H01L29/1025 ,  H01L29/1054 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66356 ,  H01L29/66969 ,  H01L29/7391 ,  H01L29/78648 ,  H01L49/003

Abstract: Tunneling field effect transistors (TFETs) including a variable bandgap channel are described. In some embodiments, one or more bandgap characteristics of the variable bandgap channel may be dynamically altered by at least one of the application or withdrawal of a force, such as a voltage or electric field. In some embodiments the variable bandgap channel may be configured to modulate from an ON to an OFF state and vice versa in response to the application and/or withdrawal of a force. The variable bandgap channel may exhibit a bandgap that is smaller in the ON state than in the OFF state. As a result, the TFETs may exhibit one or more of relatively high on current, relatively low off current, and sub-threshold swing below 60 mV/decade.

公开(公告)号：US12040378B2

公开(公告)日：2024-07-16

申请号：US17336149

申请日：2021-06-01

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Sou-Chi Chang ,  Chia-Ching Lin ,  Jack Kavalieros ,  Uygar Avci ,  Ian Young

IPC: H01L29/51 ,  H01L29/15 ,  H01L29/221 ,  H01L29/94

CPC classification number: H01L29/516 ,  H01L29/151 ,  H01L29/221 ,  H01L29/945

Abstract: Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by providing tensile stress along a plane (e.g., x-axis) of a ferroelectric or anti-ferroelectric material of the ferroelectric/anti-ferroelectric based capacitor. Tensile stress is provided by a spacer comprising metal, semimetal, or oxide (e.g., metal or oxide of one or more of: Al, Ti, Hf, Si, Ir, or N). The tensile stress provides polar orthorhombic phase to the ferroelectric material and tetragonal phase to the anti-ferroelectric material. As such, memory window and reliability of the ferroelectric/anti-ferroelectric oxide thin film improves.

公开(公告)号：US20240222483A1

公开(公告)日：2024-07-04

申请号：US18091211

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Carl H. Naylor ,  Kirby Maxey ,  Kevin O’Brien ,  Chelsey Dorow ,  Sudarat Lee ,  Ashish Verma Penumatcha ,  Uygar Avci ,  Matthew Metz ,  Scott B. Clendenning ,  Chia-Ching Lin ,  Ande Kitamura ,  Mahmut Sami Kavrik

IPC: H01L29/76 ,  H01L21/02 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/7606 ,  H01L21/02568 ,  H01L21/0257 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02645 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/775

Abstract: A transistor structure includes a stack of nanoribbons spanning between terminals of the transistor. Ends of the nanoribbons include silicon, and channel regions between the ends include a transition metal and a chalcogen. A gate structure over the channel regions includes an insulator between the channel regions and a gate electrode material. Contact regions may be formed by modifying portions of the channel regions by adding a dopant to, or altering the crystal structure of, the channel regions. The transistor structure may be in an integrated circuit device.

公开(公告)号：US20240222461A1

公开(公告)日：2024-07-04

申请号：US18091201

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Ande Kitamura ,  Carl H. Naylor ,  Kevin O'Brien ,  Kirby Maxey ,  Chelsey Dorow ,  Ashish Verma Penumatcha ,  Scott B. Clendenning ,  Uygar Avci ,  Matthew Metz ,  Chia-Ching Lin ,  Sudarat Lee ,  Mahmut Sami Kavrik ,  Carly Rogan ,  Paul Gutwin

IPC: H01L29/45 ,  H01L21/02 ,  H01L21/443 ,  H01L23/528 ,  H01L29/06 ,  H01L29/24 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/76 ,  H01L29/775

CPC classification number: H01L29/45 ,  H01L21/02568 ,  H01L21/443 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/7606 ,  H01L29/775

Abstract: A transistor in an integrated circuit (IC) die includes source and drain terminals having a bulk material enclosed by a liner material. A nanoribbon channel region couples the source and drain terminals. The nanoribbon may include a transition metal and a chalcogen. The liner material may contact ends and upper and lower surfaces of the nanoribbon. The transistor may be in an interconnect layer. The source and drain terminals may be formed by conformally depositing the liner material over the ends of the nanoribbon and in voids opened in the IC die.

公开(公告)号：US20240222126A1

公开(公告)日：2024-07-04

申请号：US18147644

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Mahmut Sami Kavrik ,  Uygar Avci ,  Brandon Holybee ,  Jennifer Lux ,  Kevin O'Brien ,  Shida Tan

IPC: H01L21/266 ,  H01L21/265

CPC classification number: H01L21/266 ,  H01L21/26506

Abstract: This disclosure describes systems, apparatus, methods, and devices related to fabrication using ion beams. The device may apply an ion beam targeted to at least one of one or more regions of a top layer, a metal layer placed on top of the top layer, or one or more ion stoppers placed on top of the top layer, wherein the ion beam is tuned using a predetermined energy range or a dosing level of ions to modify the material characteristics of the 2D material at the one or more regions of the top layer. The device may create a bond between the one or more 2D and metal layers to the one or more regions of the top layer where the material characteristics of the 2D material have been modified due to the impinging ion beam.

公开(公告)号：US20240222113A1

公开(公告)日：2024-07-04

申请号：US18091279

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Carl H. Naylor ,  Kirby Maxey ,  Kevin OBrien ,  Chelsey Dorow ,  Sudarat Lee ,  Ashish Verma Penumatcha ,  Uygar Avci ,  Matthew Metz ,  Scott B. Clendenning ,  Mahmut Sami Kavrik ,  Chia-Ching Lin ,  Ande Kitamura

IPC: H01L21/02 ,  H01L21/04 ,  H01L23/31

CPC classification number: H01L21/02568 ,  H01L21/02598 ,  H01L21/02639 ,  H01L21/045 ,  H01L23/3171

Abstract: Integrated circuit (IC) structures comprising transistors with metal chalcogenide channel material synthesized on a workpiece comprising a Group IV crystal. Prior to synthesis of the metal chalcogenide material, a passivation material is formed over the Group IV crystal to limit exposure of the substrate to the growth precursor gas(es) and thereby reduce a quantity of chalcogen species subsequently degassed from the workpiece. The passivation material may be applied to the front side, back side, and/or edge of a workpiece. The passivation material may be sacrificial or retained as a permanent feature of an IC structure. The passivation material may be advantageously amorphous and/or a compound comprising at least one of a metal or nitrogen that is good diffusion barrier and thermally stable at the metal chalcogenide synthesis temperatures.