公开(公告)号：US10056366B2

公开(公告)日：2018-08-21

申请号：US15158682

申请日：2016-05-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Theodorus E. Standaert ,  Junli Wang

IPC: H01L27/06 ,  H01L29/49 ,  H01L27/07 ,  H01L29/66 ,  H01L23/522 ,  H01L23/535 ,  H01L21/8234 ,  H01L29/06 ,  H01L49/02 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/027 ,  H01L21/3105 ,  H01L27/02

CPC classification number: H01L27/0629 ,  H01L21/0273 ,  H01L21/31051 ,  H01L21/32051 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L23/5226 ,  H01L23/535 ,  H01L27/0288 ,  H01L27/0635 ,  H01L27/0738 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/401 ,  H01L29/4238 ,  H01L29/435 ,  H01L29/4958 ,  H01L29/66545 ,  H01L29/66795

Abstract: Described herein are semiconductor devices and methods of forming the same. In some aspects, methods of forming a semiconductor device includes forming a gate stack having a self-aligning cap and a gate metal on a substrate, depositing a resist mask onto the semiconductor device, and patterning the resist mask such that the gate stack is exposed. Additionally, methods include removing the self-aligning cap and the gate metal from the exposed gate stack, depositing a resistor metal on the semiconductor device such that a metal resistor is formed within the exposed gate stack, and forming a bar contact and contact via above the metal resistor.

公开(公告)号：US20180204834A1

公开(公告)日：2018-07-19

申请号：US15846887

申请日：2017-12-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Theodorus E. Standaert ,  Junli Wang

IPC: H01L27/06 ,  H01L49/02 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L27/0629 ,  H01L21/823431 ,  H01L21/823437 ,  H01L28/24 ,  H01L29/66545 ,  H01L29/785

Abstract: A method of forming a resistor adjacent to a fin field effect transistor on a substrate, including, forming a plurality of vertical fins on the substrate, forming a dielectric fill layer on the plurality of vertical fins, forming at least two dummy gate structures on the plurality of vertical fins, forming a replaceable resistor structure on the dielectric fill layer over a region of the substrate unoccupied by vertical fins, forming a sidewall spacer on the at least two dummy gate structures and the replaceable resistor structure, removing the replaceable resistor structure to form a trench, and forming a resistor structure in the trench.

公开(公告)号：US09997407B2

公开(公告)日：2018-06-12

申请号：US15270808

申请日：2016-09-20

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan S. Basker ,  Nicolas L. Breil ,  Oleg Gluschenkov ,  Shogo Mochizuki ,  Alexander Reznicek

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L21/76883 ,  H01L21/76801 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53266 ,  H01L23/535

Abstract: Voidless contact metal structures are provided. In one embodiment, a voidless contact metal structure is provided by first providing a first contact metal that contains a void within a contact opening. The void is then opened to provide a divot in the first contact metal. After forming a dielectric spacer atop a portion of first contact metal, a second contact metal is then formed that lacks any void. The second contact metal fills the entirety of the divot within the first contact metal. In another embodiment, two diffusion barrier structures are provided within a contact opening, followed by the formation of a contact metal structure that lacks any void.

公开(公告)号：US20180158923A1

公开(公告)日：2018-06-07

申请号：US15872207

申请日：2018-01-16

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Theodorus E. Standaert ,  Junli Wang

IPC: H01L29/66 ,  H01L21/768 ,  H01L23/535 ,  H01L29/78

CPC classification number: H01L29/665 ,  H01L21/76844 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/535 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for manufacturing a semiconductor device comprises forming a silicide region on a semiconductor substrate, forming a gate structure on the semiconductor substrate adjacent the silicide region, forming a dielectric layer on the gate structure and on the silicide region, forming a first liner layer on the dielectric layer, removing a portion of the first liner layer and a portion of the dielectric layer to form an opening exposing a top surface of the silicide region, forming a second liner layer on the first liner layer and on sides and a bottom of the opening, removing a portion of the second liner layer from a top surface of the first liner layer and from the bottom of the opening to re-expose a portion of the top surface of the silicide region, and forming a contact layer in the opening directly on the re-exposed portion of the top surface of the silicide region.

公开(公告)号：US09985109B2

公开(公告)日：2018-05-29

申请号：US15333262

申请日：2016-10-25

Applicant: International Business Machines Corporation

Inventor： Emre Alptekin ,  Veeraraghavan S. Basker ,  Sivananda K. Kanakasabapathy

IPC: H01L29/66 ,  H01L21/768 ,  H01L29/06 ,  H01L29/78 ,  H01L23/535 ,  H01L29/417

CPC classification number: H01L29/665 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of fabricating a finFET semiconductor device, the method including forming a self-aligned silicide contact above and in direct contact with exposed portions of semiconductor fins not covered by a gate electrode, wherein an upper surface of the self-aligned silicide contact is substantially flush with an upper surface of an adjacent isolation region, patterning a blanket metal layer to form a source-drain contact on the upper surface of the self-aligned silicide contact, the self-aligned silicide contact provides an electrical path from the semiconductor fins to the source-drain contact, and recessing a portion of the self-aligned silicide contact without recessing the isolation region, the self-aligned silicide contact is recessed selective to a mask used to pattern the source-drain contact.

公开(公告)号：US20180145150A1

公开(公告)日：2018-05-24

申请号：US15859340

申请日：2017-12-30

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Veeraraghavan S. Basker ,  Johnathan E. Faltermeier ,  Hemanth Jagannathan ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L21/02134 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28185 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/32051 ,  H01L21/32055 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/32137 ,  H01L21/32138 ,  H01L21/47573 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66795 ,  H01L2029/7858

Abstract: A semiconductor structure includes a semiconductor substrate having an outer surface; a plurality of oxide regions, located outward of the outer surface, and defining a plurality of metal-gate-stack-receiving cavities; and a liner interspersed between the plurality of oxide regions and the semiconductor substrate and between the plurality of oxide regions and the plurality of metal-gate-stack-receiving cavities. A layer of high-K material is deposited over the semiconductor structure, including on outer surfaces of the plurality of oxide regions, outer edges of the liner, on walls of the plurality of metal-gate-stack-receiving cavities, and on the outer surface of the semiconductor substrate within the plurality of metal-gate-stack-receiving cavities. The layer of high-K material is chamfered to remove same from the outer surfaces of the plurality of oxide regions, the outer edges of the liner, and partially down the walls of the plurality of metal-gate-stack-receiving cavities.

公开(公告)号：US09966454B2

公开(公告)日：2018-05-08

申请号：US14967921

申请日：2015-12-14

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Theodorus E. Standaert ,  Junli Wang

IPC: H01L27/088 ,  H01L29/66 ,  H01L23/535 ,  H01L29/78 ,  H01L21/768

CPC classification number: H01L29/665 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for manufacturing a semiconductor device comprises forming a silicide region on a semiconductor substrate, forming a gate structure on the semiconductor substrate adjacent the silicide region, forming a dielectric layer on the gate structure and on the silicide region, forming a first liner layer on the dielectric layer, removing a portion of the first liner layer and a portion of the dielectric layer to form an opening exposing a top surface of the silicide region, forming a second liner layer on the first liner layer and on sides and a bottom of the opening, removing a portion of the second liner layer from a top surface of the first liner layer and from the bottom of the opening to re-expose a portion of the top surface of the silicide region, and forming a contact layer in the opening directly on the re-exposed portion of the top surface of the silicide region.

公开(公告)号：US20180122923A1

公开(公告)日：2018-05-03

申请号：US15845006

申请日：2017-12-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. Basker ,  Zuoguang Liu ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/3213 ,  H01L29/78 ,  H01L21/02 ,  H01L21/311 ,  H01L29/40 ,  H01L29/49

CPC classification number: H01L29/66795 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32137 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A method of forming a fin field effect transistor (finFET), including forming a temporary gate structure having a sacrificial gate layer and a dummy gate layer on the sacrificial gate layer, forming a gate spacer layer on each sidewall of the temporary gate structure, forming a source/drain spacer layer on the outward-facing sidewall of each gate spacer layer, removing the dummy gate layer to expose the sacrificial gate layer, removing the sacrificial gate layer to form a plurality of recessed cavities, and forming a gate structure, where the gate structure occupies at least a portion of the plurality of recessed cavities.

公开(公告)号：US20180114792A1

公开(公告)日：2018-04-26

申请号：US15790381

申请日：2017-10-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Sivananda K. Kanakasabapathy ,  Theodorus E. Standaert ,  Junli Wang

IPC: H01L27/11 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/02 ,  H01L29/417 ,  H01L29/45 ,  H01L29/06

CPC classification number: H01L27/1104 ,  H01L21/02167 ,  H01L21/32133 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0207 ,  H01L29/0653 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/665

Abstract: A method is presented for forming a semiconductor structure. The method includes forming gate contacts on a semiconductor substrate, forming trench silicide (TS) contacts on the semiconductor substrate, recessing the TS contacts to form a gap region, filling the gap region of the recessed TS contacts with a dielectric, selectively etching the gate contacts to form a first conducting layer, and selectively etching the TS contacts to form a second conducting layer.

公开(公告)号：US20180082904A1

公开(公告)日：2018-03-22

申请号：US15826949

申请日：2017-11-30

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Theodorus E. Standaert ,  Junli Wang

IPC: H01L21/8234 ,  H01L29/167 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/225 ,  H01L21/324 ,  H01L21/308

CPC classification number: H01L21/823431 ,  H01L21/2256 ,  H01L21/308 ,  H01L21/324 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/167 ,  H01L29/66803

Abstract: A method of making a semiconductor device includes forming a first fin of a first transistor in a substrate; forming a second fin of a second transistor in the substrate; disposing a first doped oxide layer including a first dopant onto the first fin and the second fin, the first dopant being an n-type dopant or a p-type dopant; disposing a mask over the first fin and removing the first doped oxide layer from the second fin; removing the mask and disposing a second doped oxide layer onto the first doped oxide layer over the first doped oxide layer covering the first fin and directly onto the second fin, the second doped oxide layer including an n-type dopant or a p-type dopant that is different than the first dopant; and annealing to drive in the first dopant into a portion of the first fin and the second dopant into a portion of the second fin.