公开(公告)号：US20180248021A1

公开(公告)日：2018-08-30

申请号：US15959458

申请日：2018-04-23

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Juntao Li ,  Peng Xu

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L29/66818 ,  B82Y10/00 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/02326 ,  H01L21/31116 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7853

Abstract: A method of forming a field effect transistor (FET) includes performing an oxidation on a nanosheet structure having alternating sheets of silicon and silicon germanium. An oxide etch is performed to remove portions of the sheets of silicon germanium. Other embodiments are also described herein.

公开(公告)号：US20180212017A1

公开(公告)日：2018-07-26

申请号：US15414011

申请日：2017-01-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Zhenxing Bi ,  Kangguo Cheng ,  Zheng Xu

IPC: H01L49/02 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324 ,  H01L21/283 ,  H01L21/311 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/06

CPC classification number: H01L28/60 ,  H01L21/26506 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823878 ,  H01L27/0629 ,  H01L27/092 ,  H01L28/00

Abstract: A capacitive device includes a first electrode comprising a nanosheet stack, and a second electrode comprising a nanosheet stack, the second electrode arranged substantially parallel to the first electrode. A first conductive contact is arranged on a basal end of the first electrode, and a second conductive contact arranged on a basal end of the second electrode.

公开(公告)号：US10020229B2

公开(公告)日：2018-07-10

申请号：US15487685

申请日：2017-04-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Thamarai S. Devarajan ,  Balasubramanian Pranatharthiharan

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/02 ,  H01L21/311 ,  H01L29/06 ,  H01L27/02 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823431 ,  H01L21/02274 ,  H01L21/31111 ,  H01L21/76229 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649

Abstract: A semiconductor device that includes a first plurality of fin structures in a first device region and a second plurality of fin structures in a second device region. The first plurality of fin structures includes adjacent fin structures separated by a lesser pitch than the adjacent fin structures in the second plurality of fin structures. At least one layer of dielectric material between adjacent fin structures, wherein a portion of the first plurality of fin structures extending above the at least one layer of dielectric material in the first device region is substantially equal to the portion of the second plurality of fin structures extending above the at least one layer of dielectric material in the second device region. Source and drain regions are present on opposing sides of a gate structure that is present on the fin structures.

公开(公告)号：US10020221B1

公开(公告)日：2018-07-10

申请号：US15787107

申请日：2017-10-18

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Juntao Li ,  Hao Tang

IPC: H01L27/148 ,  H01L29/80 ,  H01L29/76 ,  H01L21/00 ,  H01L21/338 ,  H01L21/762 ,  H01L29/06 ,  H01L29/78 ,  H01L21/311 ,  H01L21/3115 ,  H01L29/66

CPC classification number: H01L21/76224 ,  H01L21/31116 ,  H01L21/31155 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device includes a plurality of fins spaced apart from each other on a substrate; a liner layer on the substrate between each fin of the plurality of fins and on at least a portion of a sidewall of each fin; and a plurality of isolation regions adjacent and between the plurality of fins. The plurality of isolation regions includes a dielectric layer; and a doped region on the dielectric layer.

公开(公告)号：US20180190544A1

公开(公告)日：2018-07-05

申请号：US15795975

申请日：2017-10-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Peng Xu ,  Wenyu Xu

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/823807 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/78696

Abstract: Integrated chips include a first device and a second device. The first device includes a stack of vertically arranged sheets of a first channel material, a source and drain region having a first dopant type, and a first work function metal layer formed from a first work function metal. The second device includes a stack of vertically arranged sheets of a second channel material, a source and drain region having a second dopant type, and a second work function metal layer formed from a second work function metal.

公开(公告)号：US10002795B1

公开(公告)日：2018-06-19

申请号：US15485915

申请日：2017-04-12

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Juntao Li ,  Peng Xu

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L21/304 ,  H01L29/423 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L21/823487 ,  H01L21/823437 ,  H01L21/84 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/78642

Abstract: A method for manufacturing a semiconductor device includes forming a fin on a substrate, removing one or more portions of the fin prior to forming a gate structure on the fin, forming the gate structure on the fin, and simultaneously removing one or more additional portions of the fin and one or more portions of the gate structure aligned with the one or more additional portions of the fin to create a fin edge portion aligned with a gate structure edge portion.

公开(公告)号：US09954487B1

公开(公告)日：2018-04-24

申请号：US15288850

申请日：2016-10-07

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Hung H. Tran ,  Zheng Xu

IPC: H03B5/08 ,  H03B5/12 ,  H03L7/099 ,  H01F41/06 ,  H03H7/01 ,  H01L27/06 ,  H03H7/42 ,  H01F27/40 ,  H01F27/28

CPC classification number: H03B5/1243 ,  H01F27/2823 ,  H01F27/40 ,  H01F41/06 ,  H01L27/0676 ,  H03B5/1228 ,  H03B5/1265 ,  H03H7/0115 ,  H03H7/42 ,  H03H2210/012 ,  H03H2210/025 ,  H03J3/22 ,  H03J5/00 ,  H03J5/246 ,  H03L7/099

Abstract: A method for controlling a semiconductor circuit, including forming an inductor and a capacitor on a substrate, which are inductively coupled to one another. The inductor has an inductance value while the capacitor has a capacitance value. The inductor and capacitor make up an oscillator circuit with two terminals. Eddy currents are generated through the capacitor when an operating current flows along the inductor. These eddy currents influence, by inductive coupling, the inductance value and performance of the oscillator circuit, thus simultaneously tuning the inductance and capacitance of the oscillator circuit.

公开(公告)号：US20180096994A1

公开(公告)日：2018-04-05

申请号：US15282272

申请日：2016-09-30

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Peng Xu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823487 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545

Abstract: Semiconductor devices and methods are provided in which vertical fin resistor devices are integrally formed as part of a process flow for fabricating FinFET (Fin Field Effect Transistor) devices. For example, a semiconductor device includes a FinFET device and a vertical fin resistor device formed on a semiconductor substrate. The FinFET device includes a vertical semiconductor fin which includes a structural profile that is defined by dimensions of width W, height H, and length L. The vertical fin resistor device includes a vertical fin structure which is formed of a resistive material (e.g., polysilicon or amorphous silicon), and which has a structural profile that is defined by dimension of width W1, height H1, and length L1. The structural profiles of the vertical semiconductor fin of the FinFET device and the vertical fin structure of the vertical fin resistor device have at least one corresponding dimension that is substantially the same.

公开(公告)号：US20180090367A1

公开(公告)日：2018-03-29

申请号：US15433163

申请日：2017-02-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhenxing Bi ,  Donald F. Canaperi ,  Thamarai S. Devarajan ,  Sivananda K. Kanakasabapathy ,  Fee Li Lie ,  Peng Xu

IPC: H01L21/762 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/823481 ,  H01L21/0206 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device having a uniform height across different fin densities includes a semiconductor substrate having fins etched therein and including dense fin regions and isolation regions without fins. One or more dielectric layers are formed at a base of the fins and the isolation regions and have a uniform height across the fins and the isolation regions. The uniform height includes a less than 2 nanometer difference across the one or more dielectric layers.

公开(公告)号：US20180053716A1

公开(公告)日：2018-02-22

申请号：US15699695

申请日：2017-09-08

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Shogo Mochizuki ,  Hao Tang

IPC: H01L23/498 ,  H01L21/768 ,  H01L21/48 ,  H01L23/535 ,  H01L27/092

Abstract: A self-assembled heteroepitaxial oxide nanocomposite film including alternating layers of a first metal oxide having a first melting point and a second metal oxide having a second melting point that differs from the first melting point is formed in an opening formed in a semiconductor substrate. After forming a metal or metal alloy via structure in the semiconductor substrate, first and second thermal treatments are performed to remove each layer of first or second metal oxide providing a nanoporous membrane.