公开(公告)号：US09070849B2

公开(公告)日：2015-06-30

申请号：US14058141

申请日：2013-10-18

Applicant: Invensas Corporation

Inventor： Ilyas Mohammed ,  Liang Wang ,  Steven D. Gottke

IPC: H01L33/60 ,  H01L27/15 ,  H01L25/075 ,  H01L33/62

CPC classification number: H01L33/60 ,  F21K9/23 ,  F21Y2115/10 ,  H01L25/0753 ,  H01L27/156 ,  H01L33/62 ,  H01L2224/48463 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/19107 ,  H01L2933/0066

Abstract: In accordance with an embodiment of the present invention, an article of manufacture includes a side-emitting light emitting diode configured to emit light from more than two surfaces. The article of manufacture includes a first sheet electrically and thermally coupled to a first side of the light emitting diode, and a second sheet electrically and thermally coupled to a second side of the light emitting diode. The article of manufacture further includes a plurality of reflective surfaces configured to reflect light from all of the surfaces of the light emitting diode through holes in the first sheet. The light may be reflected via total internal reflection.

Abstract translation: 根据本发明的实施例，制品包括被配置为从多于两个表面发射光的侧面发光发光二极管。 该制品包括电和热耦合到发光二极管的第一侧的第一片，以及电耦合到发光二极管的第二侧的第二片。 制品还包括多个反射表面，其被配置为通过第一片材中的孔反射来自发光二极管的所有表面的光。 光可以通过全内反射来反射。

公开(公告)号：US20150132894A1

公开(公告)日：2015-05-14

申请号：US14600595

申请日：2015-01-20

Applicant: Invensas Corporation

Inventor： Ilyas Mohammed ,  Masud Beroz

IPC: H01L21/48 ,  H01L21/52 ,  H01L23/495 ,  H01L21/768 ,  H01L23/14

CPC classification number: H01L21/4853 ,  H01L21/486 ,  H01L21/52 ,  H01L21/768 ,  H01L23/142 ,  H01L23/49568 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00011

Abstract: Heat spreading substrate with embedded interconnects. In an embodiment in accordance with the present invention, an apparatus includes a metal parallelepiped comprising a plurality of wires inside the metal parallelepiped. The plurality of wires have a different grain structure than the metal parallelepiped. The plurality of wires are electrically isolated from the metal parallelepiped. The plurality of wires may be electrically isolated from one another.

Abstract translation: 具有嵌入式互连的散热基板。 在根据本发明的实施例中，一种装置包括金属平行六面体，其包括金属平行六面体内的多根线。 多根金属线具有与金属平行六面体不同的晶粒结构。 多个导线与金属平行六面体电绝缘。 多个电线可以彼此电隔离。

公开(公告)号：US09023691B2

公开(公告)日：2015-05-05

申请号：US13942568

申请日：2013-07-15

Applicant: Invensas Corporation

Inventor： Ilyas Mohammed ,  Belgacem Haba

IPC: H01L21/00 ,  H01L23/29 ,  H01L23/28 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/28 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/49811 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00

Abstract: A microelectronic assembly or package can include first and second support elements and a microelectronic element between inwardly facing surfaces of the support elements. First connectors and second connectors such as solder balls, metal posts, stud bumps, or the like face inwardly from the respective support elements and are aligned with and electrically coupled with one another in columns. An encapsulation separates respective pairs of coupled first and second connectors from one another and may encapsulate the microelectronic element and fill spaces between the support elements. The first connectors, the second connectors or both may be partially encapsulated prior to electrically coupling respective pairs of first and second connectors in columns.

Abstract translation: 微电子组件或封装可以包括第一和第二支撑元件以及在支撑元件的向内表面之间的微电子元件。 第一连接器和第二连接器，例如焊球，金属柱，螺柱凸起等从相应的支撑元件向内表面并且彼此对齐并且彼此电连接。 封装将各对耦合的第一和第二连接器彼此分离，并且可以封装微电子元件并填充支撑元件之间的空间。 第一连接器，第二连接器或两者可以在电耦合相应的第一和第二连接器对的列之前被部分封装。

公开(公告)号：US20150014847A1

公开(公告)日：2015-01-15

申请号：US13942568

申请日：2013-07-15

Applicant: Invensas Corporation

Inventor： Ilyas Mohammed ,  Belgacem Haba

IPC: H01L23/28 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/28 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/49811 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00

Abstract: A microelectronic assembly or package can include first and second support elements and a microelectronic element between inwardly facing surfaces of the support elements. First connectors and second connectors such as solder balls, metal posts, stud bumps, or the like face inwardly from the respective support elements and are aligned with and electrically coupled with one another in columns. An encapsulation separates respective pairs of coupled first and second connectors from one another and may encapsulate the microelectronic element and fill spaces between the support elements. The first connectors, the second connectors or both may be partially encapsulated prior to electrically coupling respective pairs of first and second connectors in columns.

Abstract translation: 微电子组件或封装可以包括第一和第二支撑元件以及在支撑元件的向内表面之间的微电子元件。 第一连接器和第二连接器，例如焊球，金属柱，螺柱凸起等从相应的支撑元件向内表面并且彼此对齐并且彼此电连接。 封装将各对耦合的第一和第二连接器彼此分离，并且可以封装微电子元件并填充支撑元件之间的空间。 第一连接器，第二连接器或两者可以在电耦合相应的第一和第二连接器对的列之前被部分封装。

公开(公告)号：US20140262457A1

公开(公告)日：2014-09-18

申请号：US13797355

申请日：2013-03-12

Applicant: INVENSAS CORPORATION

Inventor： Rajesh Katkar ,  Cyprian Emeka Uzoh ,  Belgacem Haba ,  Ilyas Mohammed

IPC: H05K1/09 ,  H05K1/11

CPC classification number: H05K1/0306 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/13 ,  H01L23/3731 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K1/09 ,  H05K1/112 ,  H05K1/115 ,  H05K3/4007 ,  H05K3/42 ,  H05K2201/09545 ,  H05K2201/10378 ,  H05K2203/0323

Abstract: Interposers and methods of making the same are disclosed herein. In one embodiment, an interposer includes a region having first and second oppositely facing surfaces and a plurality of pores, each pore extending in a first direction from the first surface towards the second surface, wherein alumina extends along a wall of each pore; a plurality of electrically conductive connection elements extending in the first direction, consisting essentially of aluminum and being electrically isolated from one another by at least the alumina; a first conductive path provided at the first surface for connection with a first component external to the interposer; and a second conductive path provided at the second surface for connection with a second component external to the interposer, wherein the first and second conductive paths are electrically connected through at least some of the connection elements.

Abstract translation: 中间体及其制备方法在本文中公开。 在一个实施例中，插入件包括具有第一和第二相对面的表面和多个孔的区域，每个孔从第一表面朝向第二表面沿第一方向延伸，其中氧化铝沿每个孔的壁延伸; 多个导电连接元件，其沿第一方向延伸，主要由铝构成，并通过至少氧化铝彼此电隔离; 第一导电路径，设置在第一表面处，用于与插入件外部的第一部件连接; 以及设置在所述第二表面处用于与所述插入件外部的第二部件连接的第二导电路径，其中所述第一和第二导电路径通过至少一些所述连接元件电连接。

公开(公告)号：US20140239514A1

公开(公告)日：2014-08-28

申请号：US13778654

申请日：2013-02-27

Applicant: INVENSAS CORPORATION

Inventor： Belgacem Haba ,  Richard Dewitt Crisp ,  Wael Zohni ,  Ilyas Mohammed

IPC: H01L23/498

CPC classification number: H01L23/5386 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/525 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip package has multiple chips that may be arranged side-by-side or in a staggered, stair step arrangement. The contacts of the chips are connected to interconnect pads carried on the chips themselves or on a redistribution substrate. The interconnect pads desirably are arranged in a relatively narrow interconnect zone, such that the interconnect pads can be readily wire-bonded or otherwise connected to a package substrate.

Abstract translation: 芯片封装具有多个芯片，可以并排布置或以交错的台阶布置布置。 芯片的触点连接到芯片本身或再分布基板上承载的互连焊盘。 互连焊盘理想地布置在相对窄的互连区域中，使得互连焊盘可以容易地线接合或以其他方式连接到封装衬底。

公开(公告)号：US20140179061A1

公开(公告)日：2014-06-26

申请号：US13722340

申请日：2012-12-20

Applicant: INVENSAS CORPORATION

Inventor： Belgacem Haba ,  Ilyas Mohammed

IPC: H01L21/56 ,  H01L21/50

CPC classification number: H01L21/56 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/50 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3107 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A first area of a first surface of an encapsulated component can be thinned, the component including: a semiconductor chip having an active surface opposite the first surface, and an encapsulant extending outwardly from edges of the semiconductor chip. An entire area of the active surface may be aligned with the first area. After the abrading, a second area of the encapsulated component beyond the first area may have a thickness greater than a thickness of the first area. The second area can be configured to fully support the abraded encapsulated component in a state of the encapsulated component being manipulated by handling equipment.

Abstract translation: 封装部件的第一表面的第一区域可以变薄，所述部件包括：具有与第一表面相对的有效表面的半导体芯片以及从半导体芯片的边缘向外延伸的密封剂。 有源表面的整个区域可以与第一区域对齐。 在研磨之后，超过第一区域的包封组分的第二区域可以具有大于第一区域的厚度的厚度。 第二区域可以被配置为在被处理设备操纵的封装部件的状态下完全支撑磨损的封装部件。

公开(公告)号：US20140014894A1

公开(公告)日：2014-01-16

申请号：US13732275

申请日：2012-12-31

Applicant: INVENSAS CORPORATION

Inventor： Ilyas Mohammed ,  Liang Wang

IPC: H01L33/38 ,  H01L33/06

CPC classification number: H01L33/62 ,  H01L33/06 ,  H01L33/382 ,  H01L33/42 ,  H01L33/502 ,  H01L33/58 ,  H01L33/60 ,  H01L33/644 ,  H01L33/647 ,  H01L2924/0002 ,  H01L2933/0066 ,  H01L2924/00

Abstract: High performance light emitting diode with vias. In accordance with a first embodiment of the present invention, an article of manufacture includes a light emitting diode. The light emitting diode includes a plurality of filled vias configured to connect a doped region on one side of the light emitting diode to a plurality of contacts on the other side of the light emitting diode. The filled vias may comprise less that 10% of a surface area of the light emitting diode.

Abstract translation: 具有通孔的高性能发光二极管。 根据本发明的第一实施例，制品包括发光二极管。 发光二极管包括多个填充的通孔，其被配置为将发光二极管的一侧上的掺杂区域连接到发光二极管的另一侧上的多个触点。 填充的通孔可以包含少于发光二极管表面积的10％。

公开(公告)号：US10813214B2

公开(公告)日：2020-10-20

申请号：US16007410

申请日：2018-06-13

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Craig Mitchell ,  Belgacem Haba ,  Ilyas Mohammed

IPC: H01K3/10 ,  H05K1/02 ,  H01L23/498 ,  H05K1/11 ,  H05K3/42 ,  H01R12/71

Abstract: A method for making an interconnection component includes forming a mask layer that covers a first opening in a sheet-like element that includes a first opening extending between the first and second surfaces of the element. The element consists essentially of a material having a coefficient of thermal expansion of less than 10 parts per million per degree Celsius. The first opening includes a central opening and a plurality of peripheral openings open to the central opening that extends in an axial direction of the central opening. A conductive seed layer can cover an interior surface of the first opening. The method further includes forming a first mask opening in at least a portion of the mask layer overlying the first opening to expose portions of the conductive seed layer within the peripheral openings; and forming electrical conductors on exposed portions of the conductive seed layer.

公开(公告)号：US10748858B2

公开(公告)日：2020-08-18

申请号：US16514104

申请日：2019-07-17

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Ilyas Mohammed ,  Masud Beroz

IPC: H01L23/00 ,  H01L21/683 ,  H01L25/00 ,  H01L33/00 ,  H01L27/02 ,  H01L21/02 ,  H01L23/544

Abstract: High yield substrate assembly. In accordance with a first method embodiment, a plurality of piggyback substrates are attached to a carrier substrate. The edges of the plurality of the piggyback substrates are bonded to one another. The plurality of piggyback substrates are removed from the carrier substrate to form a substrate assembly. The substrate assembly is processed to produce a plurality of integrated circuit devices on the substrate assembly. The processing may use manufacturing equipment designed to process wafers larger than individual instances of the plurality of piggyback substrates.