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    METHOD FOR FORMING AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE
    43.
    发明申请
    METHOD FOR FORMING AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE 失效
    用于形成片上高频电静电放电装置的方法

    公开(公告)号：US20090317970A1

    公开(公告)日：2009-12-24

    申请号：US12144089

    申请日：2008-06-23

    申请人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

    发明人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76808 ,  H01L21/7682 ,  H01L27/0248

    摘要： A method for forming an on-chip high frequency electro-static discharge device on an integrated circuit is described. In one embodiment of the method, a capped first dielectric layer with more than one electrode formed therein is provided. A second dielectric layer is deposited over the capped first dielectric layer. A first hard mask dielectric layer is deposited over the second dielectric layer. A cavity trench is formed through the first hard mask dielectric layer and the second dielectric layer to the first dielectric layer, wherein the cavity trench is formed in the first dielectric layer between two adjacent electrodes. At least one via is formed through the second dielectric layer about the cavity trench. A metal trench is formed around each of the at least one via. A release opening is formed over the cavity trench. A third dielectric layer is deposited over the second dielectric layer, wherein the third dielectric layer hermetically seals the release opening to provide electro-static discharge protection.

    摘要翻译： 描述了在集成电路上形成片上高频静电放电装置的方法。 在该方法的一个实施例中，提供了一种其上形成有多于一个电极的封盖的第一电介质层。 在封盖的第一介电层上沉积第二介电层。 第一硬掩模介电层沉积在第二介电层上。 通过第一硬掩模电介质层和第二电介质层形成腔沟槽到第一介电层，其中在两个相邻电极之间的第一电介质层中形成空腔沟槽。 至少一个通孔围绕腔沟槽形成穿过第二电介质层。 在所述至少一个通孔中的每一个周围形成金属沟槽。 在空腔沟槽上形成释放开口。 在第二电介质层上沉积第三电介质层，其中第三介电层气密地密封释放开口以提供静电放电保护。

    DESIGN STRUCTURE FOR AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE
    44.
    发明申请
    DESIGN STRUCTURE FOR AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE 有权
    片上高频电子放电装置的设计结构

    公开(公告)号：US20090316314A1

    公开(公告)日：2009-12-24

    申请号：US12144095

    申请日：2008-06-23

    申请人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

    发明人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

    IPC分类号： H02H9/00 ,  G06F17/50

    CPC分类号： H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A design structure for an on-chip high frequency electro-static discharge device is described. In one embodiment, the electro-static discharge structure comprises a first dielectric layer with more than one electrode formed therein. A second dielectric layer with more than one electrode formed therein is located above the first dielectric layer. At least one via connects the more than one electrode in the first dielectric layer with the more than one electrode in the second dielectric layer. A gap is formed through the first dielectric layer and the second dielectric layer, wherein the gap extends between two adjacent electrodes in both the first dielectric layer and the second dielectric layer. A third dielectric layer is disposed over the second dielectric layer, wherein the third dielectric layer hermetically seals the gap to provide electro-static discharge protection on the integrated circuit.

    摘要翻译： 描述了片上高频静电放电装置的设计结构。 在一个实施例中，静电放电结构包括其中形成有多于一个电极的第一电介质层。 其中形成有多于一个电极的第二电介质层位于第一介电层的上方。 至少一个通孔将第一介电层中的多于一个的电极与第二介电层中的多于一个的电极连接。 通过第一电介质层和第二电介质层形成间隙，其中间隙在第一电介质层和第二电介质层中的两个相邻电极之间延伸。 第三电介质层设置在第二电介质层上，其中第三介电层气密地密封间隙以在集成电路上提供静电放电保护。

    Methods for selective reverse mask planarization and interconnect structures formed thereby
    47.
    发明授权
    Methods for selective reverse mask planarization and interconnect structures formed thereby 失效
    用于选择性反向掩模平面化和由此形成的互连结构的方法

    公开(公告)号：US08710661B2

    公开(公告)日：2014-04-29

    申请号：US12323512

    申请日：2008-11-26

    申请人： Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

    发明人： Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

    IPC分类号： H01L23/522

    CPC分类号： H01L23/528 ,  H01L21/31056 ,  H01L21/76819 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods for planarizing layers of a material, such as a dielectric, and interconnect structures formed by the planarization methods. The method includes depositing a first dielectric layer on a top surface of multiple conductive features and on a top surface of a substrate between the conductive features. A portion of the first dielectric layer is selectively removed from the top surface of at least one of the conductive features without removing a portion the first dielectric layer that is between the conductive features. A second dielectric layer is formed on the top surface of the at least one of the conductive features and on a top surface of the first dielectric layer, and a top surface of the second dielectric layer is planarized. A layer operating as an etch stop is located between the top surface of at least one of the conductive features and the second dielectric layer.

    摘要翻译： 用于平坦化诸如电介质的材料层的平面化方法以及通过平面化方法形成的互连结构。 该方法包括在多个导电特征的顶表面和导电特征之间的衬底的顶表面上沉积第一介电层。 第一介电层的一部分从至少一个导电特征的顶表面选择性地去除，而不去除导电特征之间的第一介电层的一部分。 第二电介质层形成在至少一个导电特征的顶表面上和第一介电层的顶表面上，并且第二介电层的顶表面被平坦化。 作为蚀刻停止件操作的层位于导电特征中的至少一个的顶表面和第二介电层之间。

    Structure and design structure for high-Q value inductor and method of manufacturing the same
    48.
    发明授权
    Structure and design structure for high-Q value inductor and method of manufacturing the same 有权
    高Q值电感器的结构和设计结构及其制造方法

    公开(公告)号：US08645898B2

    公开(公告)日：2014-02-04

    申请号：US13535412

    申请日：2012-06-28

    申请人： Hanyi Ding ,  Mete Erturk ,  Robert A. Groves ,  Zhong-Xiang He ,  Peter J. Lindgren ,  Anthony K. Stamper

    发明人： Hanyi Ding ,  Mete Erturk ,  Robert A. Groves ,  Zhong-Xiang He ,  Peter J. Lindgren ,  Anthony K. Stamper

    IPC分类号： G06F17/50 ,  H01L27/08

    CPC分类号： H01L28/10 ,  H01L21/76898 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

    摘要： Structures with high-Q value inductors, design structure for high-Q value inductors and methods of fabricating such structures is disclosed herein. A method in a computer-aided design system for generating a functional design model of an inductor is also provided. The method includes: generating a functional representation of a plurality of vertical openings simultaneously formed in a substrate, wherein a first of the plurality of vertical openings is used as through silicon vias and is etched deeper than a second of the plurality of vertical openings used for high-Q inductors; generating a functional representation of a dielectric layer formed in the plurality of vertical openings; and generating a functional representation of a metal layer deposited on the dielectric layer in the plurality of vertical.

    摘要翻译： 具有高Q值电感器的结构，高Q值电感器的设计结构和制造这种结构的方法在本文中公开。 还提供了一种用于产生电感器的功能设计模型的计算机辅助设计系统中的方法。 该方法包括：产生同时形成在衬底中的多个垂直开口的功能表示，其中多个垂直开口中的第一个用作通过硅通孔，并且被蚀刻比用于多个垂直开口 高Q电感; 产生形成在所述多个垂直开口中的电介质层的功能性表示; 以及生成沉积在所述多个垂直方向上的所述电介质层上的金属层的功能表示。

    Method of electrolytic plating and semiconductor device fabrication
    49.
    发明授权
    Method of electrolytic plating and semiconductor device fabrication 有权
    电解电镀和半导体器件制造方法

    公开(公告)号：US08518817B2

    公开(公告)日：2013-08-27

    申请号：US12887737

    申请日：2010-09-22

    申请人： Felix P. Anderson ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

    发明人： Felix P. Anderson ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/7684 ,  C25D3/38 ,  C25D5/10 ,  C25D5/12 ,  H01L21/2885 ,  H01L21/76877

    摘要： The disclosure relates generally to semiconductor device fabrication, and more particularly to methods of electroplating used in semiconductor device fabrication. A method of electroplating includes: immersing an in-process substrate into an electrolytic plating solution to form a first metal layer on the in-process substrate; then performing a first chemical-mechanical polish to a liner on the in-process substrate followed by immersing the in-process substrate into the electrolytic plating solution to form a second metal layer on the first metal layer and the liner; and performing a second chemical-mechanical polish to the liner.

    摘要翻译： 本公开一般涉及半导体器件制造，更具体地涉及用于半导体器件制造中的电镀方法。 电镀方法包括：将处理后的基板浸入电解镀液中以在工艺衬底上形成第一金属层; 然后对所述工艺衬底上的衬垫进行第一化学机械抛光，然后将所述工艺衬底浸入所述电解电镀溶液中，以在所述第一金属层和所述衬垫上形成第二金属层; 以及对所述衬垫执行第二化学机械抛光。

    Semiconductor structures and methods of manufacture
    50.
    发明授权
    Semiconductor structures and methods of manufacture 有权
    半导体结构及制造方法

    公开(公告)号：US08497203B2

    公开(公告)日：2013-07-30

    申请号：US12856212

    申请日：2010-08-13

    申请人： Fen Chen ,  Zhong-Xiang He ,  Anthony K. Stamper

    发明人： Fen Chen ,  Zhong-Xiang He ,  Anthony K. Stamper

    IPC分类号： H01L21/4703

    CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L21/76834 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Semiconductor structures with airgaps and/or metal linings and methods of manufacture are provided. The method of forming an airgap in a wiring level includes forming adjacent wires in a dielectric layer. The method further includes forming a masking layer coincident with the adjacent wire and forming a first layer on the masking layer to reduce a size of an opening formed in the masking layer between the adjacent wires. The method further includes removing exposed portions of the first layer and the dielectric layer to form trenches between the adjacent wires. The method further includes forming an interlevel dielectric layer upon the dielectric layer, where the interlevel dielectric layer is pinched off from filling the trenches so that an airgap is formed between the adjacent wires. A metal liner can also be formed in the trenches, prior to the formation of the airgap.

    摘要翻译： 提供具有气隙和/或金属衬里和制造方法的半导体结构。 在布线层中形成气隙的方法包括在电介质层中形成相邻的布线。 该方法还包括形成与相邻导线重合的掩模层，并在掩模层上形成第一层以减小形成在相邻导线之间的掩模层中的开口的尺寸。 该方法还包括去除第一层和电介质层的暴露部分以在相邻导线之间形成沟槽。 所述方法还包括在所述电介质层上形成层间电介质层，其中夹层所述层间电介质层以填充所述沟槽，使得在相邻导线之间形成气隙。 在形成气隙之前，也可以在沟槽中形成金属衬垫。