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80 条记录 (耗时 0.034 秒)

    Memory/logic conjugate system
    43.
    发明授权
    Memory/logic conjugate system 失效
    存储器/逻辑共轭系统

    公开(公告)号：US08305789B2

    公开(公告)日：2012-11-06

    申请号：US12977243

    申请日：2010-12-23

    申请人： Kanji Otsuka ,  Tsuneo Ito ,  Yoichi Sato ,  Masahiro Yoshida ,  Shigeru Yamamoto ,  Takeshi Koyama ,  Yuko Tanba ,  Yutaka Akiyama

    发明人： Kanji Otsuka ,  Tsuneo Ito ,  Yoichi Sato ,  Masahiro Yoshida ,  Shigeru Yamamoto ,  Takeshi Koyama ,  Yuko Tanba ,  Yutaka Akiyama

    IPC分类号： G11C5/06

    CPC分类号： G06F13/4022 ,  G11C5/02 ,  G11C7/1006 ,  G11C2213/71

    摘要： A bandwidth bottleneck occurs because a crossbar switch is used to cope with an increase in scale. A memory/logic conjugate system according to the present invention, a plurality of cluster memory chips each including a plurality of cluster memories 20 including basic cells 10 arranged in a cluster, the basic cell 10 including a memory circuit, and a controller chip that controls the plurality of cluster memories are three-dimensionally stacked, the plurality of cluster memories 20 located along the stacking direction of the plurality of cluster memory chips and the controller chip are electrically coupled to the controller chip via a multibus 11 including a through-via, an arbitrary one of the basic cells 10 is directly accessed through the multibus 11 from the controller chip so that truth value data is written therein, and whereby the arbitrary basic cell 10 is switched to a logic circuit as conjugate.

    摘要翻译： 发生带宽瓶颈是因为使用横杠开关来应对规模的增加。 根据本发明的存储器/逻辑共轭系统，多个集群存储器芯片，每个集群存储器芯片包括多个集群存储器20，集群存储器20包括布置在集群中的基本单元10，基本单元10包括存储器电路，以及控制芯片， 多个集群存储器是三维堆叠的，沿着多个集群存储器芯片的堆叠方向定位的多个集群存储器20和控制器芯片经由包括通孔的多通道11电耦合到控制器芯片， 基本单元10中的任意一个基本单元10通过多轴11从控制器芯片直接访问，从而将真值数据写入其中，并且由此将任意基本单元10切换到逻辑电路作为共轭。

    WIRING AND COMPOSITE WIRING
    44.
    发明申请
    WIRING AND COMPOSITE WIRING 审中-公开
    接线和复合接线

    公开(公告)号：US20110042120A1

    公开(公告)日：2011-02-24

    申请号：US12865555

    申请日：2009-02-02

    申请人： Kanji Otsuka ,  Tamotsu Usami ,  Chihiro Ueda ,  Yutaka Akiyama

    发明人： Kanji Otsuka ,  Tamotsu Usami ,  Chihiro Ueda ,  Yutaka Akiyama

    IPC分类号： H01B11/02

    CPC分类号： H01P3/00

    摘要： A wire (a twisted pair cable) that transmits a gigahertz band signal and that is provided with a pair of core wires that are twisted with each other, a first insulation coating material, a second insulation coating material, and a shield material that shields evanescent waves emitted from the pair of core wires. The pair of core wires have a twisting pitch, a diameter, and a spacing so that the wire has a characteristic impedance of 100 to 200Ω and the phases of the TEM (Transverse Electro-Magnetic) wave and the evanescent wave that are emitted from the pair of core wires are matched.

    摘要翻译： 一根传输千兆赫兹信号的线（双绞线），并设置有一对互相绞合的芯线，第一绝缘涂层材料，第二绝缘涂层材料和屏蔽材料， 从一对芯线发射的波。 一对芯线具有扭曲间距，直径和间距，使得导线具有100至200Ω的特征阻抗; 并且从一对芯线发射的TEM（横向电磁）波和ev逝波的相位匹配。

    PRINTED CIRCUIT BOARD
    45.
    发明申请
    PRINTED CIRCUIT BOARD 有权
    印刷电路板

    公开(公告)号：US20100013318A1

    公开(公告)日：2010-01-21

    申请号：US12501931

    申请日：2009-07-13

    申请人： Daisuke Iguchi ,  Kanji Otsuka ,  Yutaka Akiyama

    发明人： Daisuke Iguchi ,  Kanji Otsuka ,  Yutaka Akiyama

    IPC分类号： H05K9/00

    CPC分类号： H05K9/0084 ,  H05K1/0218 ,  H05K1/0234 ,  H05K1/167 ,  H05K3/403 ,  H05K2201/0187 ,  H05K2201/0215 ,  H05K2201/09309

    摘要： A printed circuit board includes a ground layer, a power source layer, a signal wiring layer, an insulating layer and an electromagnetic radiation suppressing member. The power source layer is provided to be opposed to the ground layer. The signal wiring layer transmits a signal in a predetermined frequency domain. The insulating layer insulates the ground layer, the power source layer and the signal wiring layer from one another. The electromagnetic radiation suppressing member is provided to cover a circumferential edge of the insulating layer. The electromagnetic radiation suppressing member has a negative dielectric constant and a positive magnetic permeability in a frequency domain including the predetermined frequency domain.

    摘要翻译： 印刷电路板包括接地层，电源层，信号布线层，绝缘层和电磁辐射抑制构件。 电源层设置成与接地层相对。 信号布线层发送预定频域的信号。 绝缘层使接地层，电源层和信号布线层彼此绝缘。 电磁辐射抑制构件被设置成覆盖绝缘层的周缘。 电磁辐射抑制构件在包括预定频域的频域中具有负介电常数和正磁导率。

    Electrostatic discharge protection circuit and terminating resistor circuit
    47.
    发明申请
    Electrostatic discharge protection circuit and terminating resistor circuit 有权
    静电放电保护电路和终端电阻电路

    公开(公告)号：US20080042686A1

    公开(公告)日：2008-02-21

    申请号：US11819579

    申请日：2007-06-28

    申请人： Kanji Otsuka ,  Tamotsu Usami ,  Yutaka Akiyama ,  Tsuneo Ito ,  Yuko Tanba

    发明人： Kanji Otsuka ,  Tamotsu Usami ,  Yutaka Akiyama ,  Tsuneo Ito ,  Yuko Tanba

    IPC分类号： H03K19/003 ,  H02H9/04

    CPC分类号： H01L27/0266

    摘要： Disclosed is an electrostatic discharge protection circuit capable of realizing speeding up of differential signals by reducing a capacitance of the circuit. Transmission lines are connected to an IN terminal and an IN Bar terminal and differential signals are input to the terminals. The ESD protection circuit is connected to the transmission lines and protects an internal circuit from a surge voltage applied to the IN terminal and the IN Bar terminal. A pair of transistors of the ESD protection circuit is formed in the same well. Thereby, when differential signals transit, charges in drains of the pair of transistors holding a state before a transition transfer in the same well. As a result, the capacitances in the drains of the pair of transistors are reduced with respect to the transition of differential signals so that the speeding up of differential signals can be realized.

    摘要翻译： 公开了一种能够通过减小电路的电容来实现差分信号的加速的静电放电保护电路。 传输线连接到IN端子，IN条形端子和差分信号输入端子。 ESD保护电路连接到传输线，并保护内部电路免受施加到IN端子和IN Bar端子的浪涌电压。 ESD保护电路的一对晶体管形成在同一个阱中。 因此，当差分信号传输时，在同一井内转移转移之前保持状态的一对晶体管的漏极中的电荷。 结果，一对晶体管的漏极中的电容相对于差分信号的转变而减小，从而可以实现差分信号的加速。

    Semiconductor memory device
    50.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US20060203586A1

    公开(公告)日：2006-09-14

    申请号：US11360681

    申请日：2006-02-24

    申请人： Kanji Otsuka ,  Tamotsu Usami

    发明人： Kanji Otsuka ,  Tamotsu Usami

    IPC分类号： G11C7/00

    CPC分类号： H01L27/108 ,  G11C5/063 ,  G11C7/12 ,  G11C7/18 ,  G11C11/405 ,  G11C11/4094 ,  G11C11/4097

    摘要： A memory cell MC includes nMOS transistors for a transfer gate configured to be paired with each other, and one capacitor for data storage connected to the nMOS transistor. A gate electrode of the nMOS transistor is connected to a word line WL, and a drain is connected to a bit line BL. A gate electrode of the nMOS transistor is connected to a word line /WL, and a drain and a source are connected to a ground. The capacitor is connected between a source of the nMOS transistor and the ground. A Y selector circuit is connected between a differential bit line BL, /BL and a differential data line DL, /DL. The Y selector circuit has two pairs of nMOS transistors configured to be paired transistors, respectively.

    摘要翻译： 存储单元MC包括用于被配置为彼此配对的传输门的nMOS晶体管，以及连接到nMOS晶体管的一个用于数据存储的电容器。 nMOS晶体管的栅电极连接到字线WL，漏极连接到位线BL。 nMOS晶体管的栅电极连接到字线/ WL，漏极和源极连接到地。 电容器连接在nMOS晶体管的源极和地之间。 Y选择电路连接在差分位线BL，/ BL和差分数据线DL / DL之间。 Y选择器电路具有分别配置为成对晶体管的两对nMOS晶体管。