公开(公告)号：US20140268616A1

公开(公告)日：2014-09-18

申请号：US13833632

申请日：2013-03-15

Applicant: QUALCOMM INCORPORATED

Inventor： Je-Hsiung Lan ,  Chengjie Zuo ,  Changhan Yun ,  David F. Berdy ,  Daeik D. Kim ,  Robert P. Mikulka ,  Mario Francisco Velez ,  Jonghae Kim

IPC: H01L49/02 ,  G06F17/50

CPC classification number: H01L28/40 ,  G06F17/5068 ,  H01L23/15 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L27/016 ,  H01L27/12 ,  H01L28/10 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a particular embodiment, a device includes a substrate, a via that extends at least partially through the substrate, and a capacitor. A dielectric of the capacitor is located between the via and a plate of the capacitor, and the plate of the capacitor is external to the substrate and within the device.

Abstract translation: 在特定实施例中，器件包括衬底，至少部分延伸穿过衬底的通孔和电容器。 电容器的电介质位于电容器的通孔和板之间，并且电容器的板在衬底外部和器件内部。

公开(公告)号：US20140167273A1

公开(公告)日：2014-06-19

申请号：US13719984

申请日：2012-12-19

Applicant: QUALCOMM INCORPORATED

Inventor： Jonghae Kim ,  Chengjie Zuo ,  Changhan Yun ,  Mario Francisco Velez ,  Ravindra V. Shenoy ,  Matthew M. Nowak ,  Francesco Carobolante ,  Kyu-Pyung Hwang ,  Dong Wook Kim ,  Young K. Song

IPC: H01L23/482 ,  H01L23/00

CPC classification number: H01L21/6836 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L2221/68345 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/1517 ,  H01L2924/181 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/10015 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00

Abstract: One feature pertains to a multi-layer package substrate of an integrated circuit package that comprises a discrete circuit component (DCC) having at least one electrode. The DCC is embedded within an insulator layer, and a via coupling component electrically couples to the electrode. A first portion of the via coupling component extends beyond a first edge of the electrode, and a plurality of vias each having a first end couple to the first via coupling component. At least a first via of the plurality of vias couples to the first portion of the via coupling component that extends beyond the first edge of the electrode. Moreover, the plurality of vias each have a second end that electrically couple to a first outer metal layer, and at least a second portion of the via coupling component is positioned within a first inner metal layer.

Abstract translation: 一个特征涉及集成电路封装的多层封装衬底，其包括具有至少一个电极的分立电路部件（DCC）。 DCC嵌入在绝缘体层内，并且通孔耦合部件电耦合到电极。 通孔耦合部件的第一部分延伸超过电极的第一边缘，并且多个通孔各自具有耦合到第一通路耦合部件的第一端。 多个通孔中的至少第一通孔耦合到延伸超出电极的第一边缘的通孔连接部件的第一部分。 此外，多个通孔各自具有电耦合到第一外部金属层的第二端，并且通孔连接部件的至少第二部分位于第一内部金属层内。

公开(公告)号：US20140138792A1

公开(公告)日：2014-05-22

申请号：US13684103

申请日：2012-11-21

Applicant: QUALCOMM INCORPORATED

Inventor： Chi Shun Lo ,  Je-Hsiung Lan ,  Mario Francisco Velez ,  Jonghae Kim

IPC: H01L49/02 ,  H01L21/00

CPC classification number: H01L28/10 ,  H01F19/04 ,  H01F21/00 ,  H01F2019/085 ,  H01F2027/2809 ,  H01L21/00 ,  H01L23/5227 ,  H01L23/645 ,  H01L2924/0002 ,  Y10T29/41 ,  H01L2924/00

Abstract: Several novel features pertain to a hybrid transformer formed within a semiconductor die having multiple layers. The hybrid transformer includes a first set of windings positioned on a first layer of the die. The first layer is positioned above a substrate of the die. The first set of windings includes a first port and a second port. The first set of windings is arranged to operate as a first inductor. The hybrid transformer includes a second set of windings positioned on a second layer of the die. The second layer is positioned above the substrate. The second set of windings includes a third port, a fourth port and a fifth port. The second set of windings is arranged to operate as a second inductor and a third inductor. The first set of windings and the second set of windings are arranged to operate as a vertical coupling hybrid transformer.

Abstract translation: 几种新颖的特征涉及形成在具有多层的半导体管芯内的混合变压器。 混合变压器包括位于模具的第一层上的第一组绕组。 第一层位于模具的基底之上。 第一组绕组包括第一端口和第二端口。 第一组绕组被布置成作为第一电感器工作。 混合变压器包括位于模具的第二层上的第二组绕组。 第二层位于衬底上方。 第二组绕组包括第三端口，第四端口和第五端口。 第二组绕组被布置成用作第二电感器和第三电感器。 第一组绕组和第二组绕组被布置成作为垂直耦合混合变压器工作。

公开(公告)号：US11024454B2

公开(公告)日：2021-06-01

申请号：US15191203

申请日：2016-06-23

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Mario Francisco Velez ,  Changhan Hobie Yun ,  Niranjan Sunil Mudakatte ,  Jonghae Kim ,  Chengjie Zuo ,  David Francis Berdy

IPC: H01F5/00 ,  H01F27/28 ,  H01F41/04 ,  H03H7/01 ,  H03F15/00 ,  H01F17/00 ,  H01F27/24

Abstract: Disclosed is an inductor device including a first curved metal plate, a second curved metal plate below and substantially vertically aligned with the first curved metal plate, and a first elongated via vertically aligned between the first curved metal plate and the second curved metal plate, the first elongated via configured to conductively couple the first curved metal plate to the second curved metal plate and having an aspect ratio of a width to a height of the first elongated via of at least approximately 2 to 1.

公开(公告)号：US11003884B2

公开(公告)日：2021-05-11

申请号：US15430389

申请日：2017-02-10

Applicant: QUALCOMM Incorporated

Inventor： Nicholas Ian Buchan ,  Mario Francisco Velez ,  Chin-Jen Tseng ,  Hrishikesh Vijaykumar Panchawagh ,  Firas Sammoura ,  Jessica Liu Strohmann ,  Kostadin Dimitrov Djordjev ,  David William Burns ,  Leonard Eugene Fennell ,  Jon Gregory Aday

IPC: G06K9/00 ,  G01N29/22 ,  G01N29/24 ,  H01L41/047 ,  H01L41/107 ,  G02F1/1333 ,  H01L27/32

Abstract: A fingerprint sensor device includes a sensor substrate, a plurality of sensor circuits over a first surface of the sensor substrate, and a transceiver layer located over the plurality of sensor circuits and the first surface of the sensor substrate. The transceiver layer includes a piezoelectric layer and a transceiver electrode positioned over the piezoelectric layer. The piezoelectric layer and the transceiver electrode are configured to generate one or more ultrasonic waves or to receive one or more ultrasonic waves. The fingerprint sensor device may include a cap coupled to the sensor substrate and a cavity formed between the cap and the sensor substrate. The cavity and the sensor substrate may form an acoustic barrier.

公开(公告)号：US10582609B2

公开(公告)日：2020-03-03

申请号：US15798071

申请日：2017-10-30

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie Yun ,  Jonghae Kim ,  Xiaoju Yu ,  Mario Francisco Velez ,  Wei-Chuan Chen ,  Niranjan Sunil Mudakatte ,  Matthew Michael Nowak ,  Christian Hoffmann ,  Rodrigo Pacher Fernandes ,  Manuel Hofer ,  Peter Bainschab ,  Edgar Schmidhammer ,  Stefan Leopold Hatzl

IPC: H05K1/02 ,  H05K3/32 ,  H03H9/02 ,  H03H9/10 ,  H03H3/02 ,  H03H9/05 ,  H03H3/08

Abstract: A passive on glass (POG) on filter capping apparatus may include an acoustic filter die. The apparatus may further include a capping die electrically coupled to the acoustic filter die. The capping die may include a 3D inductor.

公开(公告)号：US10292269B1

公开(公告)日：2019-05-14

申请号：US15950865

申请日：2018-04-11

Applicant: QUALCOMM Incorporated

Inventor： Niranjan Sunil Mudakatte ,  Changhan Hobie Yun ,  Jonghae Kim ,  Xiaoju Yu ,  Nosun Park ,  Mario Francisco Velez

IPC: H05K1/16 ,  H05K1/18 ,  H01L23/522 ,  H03H7/01 ,  H01L23/66 ,  H01L49/02

Abstract: An inductor-capacitor (LC) filter includes an inductor having an asymmetric shape including at least one turn. The LC filter also includes serial capacitors coupled to the inductor at only one end of a continuous portion of the inductor. The serial capacitors continues the shape of the inductor. The capacitors are outside of a footprint of the continuous portion of the inductor.

公开(公告)号：US10049815B2

公开(公告)日：2018-08-14

申请号：US15167782

申请日：2016-05-27

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Jonghae Kim ,  Chengjie Zuo ,  Mario Francisco Velez ,  Changhan Hobie Yun

IPC: H01F41/04 ,  H01F27/28 ,  H01F41/00 ,  H01F17/00

Abstract: A 3D nested transformer includes a substrate having a set of through substrate vias daisy chained together with a set of traces. At least some of the through substrate vias have first and second conductive regions. The set of traces also includes a first set of traces coupling together at least some of the first conductive regions of the through substrate vias, and a second set of traces coupling together at least some of the second conductive regions of the through substrate vias.

公开(公告)号：US10039188B2

公开(公告)日：2018-07-31

申请号：US14811813

申请日：2015-07-28

Applicant: QUALCOMM Incorporated

Inventor： Changhan Yun ,  Francesco Carobolante ,  Chengjie Zuo ,  Jonghae Kim ,  Mario Francisco Velez ,  Lawrence D. Smith ,  Matthew M. Nowak

IPC: H05K1/16 ,  H05K1/02 ,  H01L23/498 ,  H05K7/10 ,  H05K3/10 ,  H05K3/30 ,  H05K3/00

CPC classification number: H05K1/165 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/19105 ,  H05K1/0231 ,  H05K1/0243 ,  H05K1/0262 ,  H05K3/0091 ,  H05K3/10 ,  H05K3/30 ,  H05K7/1092 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49147 ,  Y10T29/49156

Abstract: A two-stage power delivery network includes a voltage regulator and an interposer. The interposer includes a packaging substrate having an embedded inductor. The embedded inductor includes a set of traces and a set of through substrate vias at opposing ends of the traces. The interposer is coupled to the voltage regulator. The two-stage power delivery network also includes a semiconductor die supported by the packaging substrate. The two-stage power delivery network also includes a capacitor that is supported by the packaging substrate. The capacitor is operable to provide a decoupling capacitance associated with the semiconductor die and a capacitance to reduce a switching noise of the voltage regulator.

公开(公告)号：US09875848B2

公开(公告)日：2018-01-23

申请号：US14976973

申请日：2015-12-21

Applicant: QUALCOMM Incorporated

Inventor： David Francis Berdy ,  Daeik Daniel Kim ,  Niranjan Sunil Mudakatte ,  Je-Hsiung Jeffrey Lan ,  Chengjie Zuo ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Jonghae Kim

IPC: H01G4/30 ,  H01L23/52 ,  H01G4/01 ,  H01G4/33 ,  H01L23/522 ,  H01L27/08 ,  H01L29/94 ,  H01L49/02

CPC classification number: H01G4/30 ,  H01G4/01 ,  H01G4/33 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/86 ,  H01L28/87 ,  H01L29/94

Abstract: An exemplary MIM capacitor may include a first metal plate, a dielectric layer on the first metal plate, a second metal plate on the dielectric layer, a via layer on the second metal plate, and a third metal plate on the via layer where the second metal plate has a tapered outline with a first side and a second side longer than the first side such that the second side provides a lower resistance path for a current flow.