公开(公告)号：US09704796B1

公开(公告)日：2017-07-11

申请号：US15041853

申请日：2016-02-11

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Shree Krishna Pandey ,  Ratibor Radojcic

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/5389 ,  H01L23/642 ,  H01L24/17 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16268 ,  H01L2224/18 ,  H01L2924/05042 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19102

Abstract: Some features pertain to an integrated device that includes a die and a first redistribution portion coupled to the die. The first redistribution portion includes at least one dielectric layer and a capacitor. The capacitor includes a first plate, a second plate, and an insulation layer located between the first plate and the second plate. The first redistribution portion further includes several first pins coupled to the first plate of the capacitor. The first redistribution portion further includes several second pins coupled to the second plate of the capacitor. In some implementations, the capacitor includes the first pins and/or the second pins. In some implementations, at least one pin from the several first pins traverses through the second plate to couple to the first plate of the capacitor. In some implementations, the second plate comprises a fin design.

公开(公告)号：US20170084531A1

公开(公告)日：2017-03-23

申请号：US14861958

申请日：2015-09-22

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Daeik Daniel Kim ,  Matthew Michael Nowak ,  Jonghae Kim ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  David Francis Berdy

IPC: H01L23/498 ,  H01L21/8234 ,  H01L21/306 ,  H01L27/088 ,  H01L27/12 ,  H01L23/66 ,  H01L21/84 ,  H01L21/304

CPC classification number: H01L27/1203 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/76251 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/49894 ,  H01L23/528 ,  H01L23/66 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1222 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1266 ,  H01L29/1087 ,  H01L29/66772

Abstract: An integrated circuit (IC) includes a first semiconductor device on a glass substrate. The first semiconductor device includes a first semiconductive region of a bulk silicon wafer. The IC includes a second semiconductor device on the glass substrate. The second semiconductor device includes a second semiconductive region of the bulk silicon wafer. The IC includes a through substrate trench between the first semiconductive region and the second semiconductive region. The through substrate trench includes a portion disposed beyond a surface of the bulk silicon wafer.

公开(公告)号：US09466554B2

公开(公告)日：2016-10-11

申请号：US14274517

申请日：2014-05-09

Applicant: QUALCOMM Incorporated

Inventor： Jae Sik Lee ,  Hong Bok We ,  Dong Wook Kim ,  Shiqun Gu

IPC: H01L21/4763 ,  H01L23/48 ,  H01L23/50 ,  H01L21/56 ,  H01L21/768 ,  H01L23/498 ,  H01L25/10 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/49827 ,  H01L23/50 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/1533

Abstract: Some novel features pertain to an integrated device that includes an encapsulation layer, a via structure traversing the encapsulation layer, and a pad. The via structure includes a via that includes a first side, a second side, and a third side. The via structure also includes a barrier layer surrounding at least the first side and the third side of the via. The pad is directly coupled to the barrier layer of the via structure. In some implementations, the integrated device includes a first dielectric layer coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a substrate coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a first die coupled to the substrate, where the encapsulation layer encapsulates the first die. In some implementations, the via includes a portion configured to operate as a pad.

Abstract translation: 一些新颖的特征涉及包括封装层，穿过封装层的通孔结构和衬垫的集成器件。 通孔结构包括通孔，其包括第一侧，第二侧和第三侧。 通孔结构还包括至少围绕通孔的第一侧和第三侧的阻挡层。 焊盘直接耦合到通孔结构的阻挡层。 在一些实施方案中，集成器件包括耦合到封装层的第一表面的第一介电层。 在一些实施方案中，集成器件包括耦合到封装层的第一表面的衬底。 在一些实施方案中，集成器件包括耦合到衬底的第一管芯，其中封装层封装第一管芯。 在一些实施方式中，通孔包括被配置为作为垫进行操作的部分。

公开(公告)号：US09425096B2

公开(公告)日：2016-08-23

申请号：US14330950

申请日：2014-07-14

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Matthew Michael Nowak ,  Jeffrey Junhao Xu

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/14 ,  H01L23/498

CPC classification number: H01L21/76895 ,  H01L21/7682 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5222 ,  H01L23/53257 ,  H01L23/53295 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Systems and methods are directed to a semiconductor device, which includes an integrated circuit, wherein the integrated circuit includes at least a first layer comprising two or more Tungsten lines and at least one air gap between at least two Tungsten lines, the air gaps to reduce capacitance. An interposer is coupled to the integrated circuit, to reduce stress on the two or more Tungsten lines and the at least one air gap. A laminated package substrate may be attached to the interposer such that the interposer is configured to absorb mechanical stress induced by mismatch in coefficient of thermal expansion (CTE) between the laminated package substrate and the interposer and protect the air gap from the mechanical stress.

Abstract translation: 系统和方法涉及包括集成电路的半导体器件，其中集成电路至少包括包含两条或更多条钨线的至少一条第一层和至少两条钨线之间的至少一个气隙，所述气隙减少 电容。 插入器耦合到集成电路，以减少两个或多个钨线和至少一个气隙的应力。 层叠封装基板可以附接到插入件，使得插入件被构造成吸收由层压封装基板和插入件之间的热膨胀系数（CTE）失配引起的机械应力，并保护气隙免受机械应力。

公开(公告)号：US09401350B1

公开(公告)日：2016-07-26

申请号：US14812476

申请日：2015-07-29

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Jae Sik Lee ,  Dong Wook Kim ,  Shiqun Gu

IPC: H01L25/18 ,  H01L23/522 ,  H01L23/532 ,  H01L21/56 ,  H01L21/768 ,  H01L25/00 ,  H01L21/52 ,  H01L23/00 ,  H01L23/528 ,  H01L23/31

CPC classification number: H01L21/52 ,  H01L21/4846 ,  H01L21/568 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2924/1432 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A package-on-package (POP) structure is disclosed. The POP structure includes a first die, a second die, and a photo-imaged dielectric (PID) layer. The PID layer is disposed between the first die and the second die. The POP structure also includes a first conductive path from the first die through the PID layer to the second die. The first conductive path extends directly through a first area of the PID layer directly between the first die and the second die. The POP structure further includes a second conductive path from the first die through the PID layer to the second die. A particular portion of the second conductive path is perpendicular to the first conductive path and extends through a second area of the PID layer not directly between the first die and the second die.

Abstract translation: 公开了一种封装封装（POP）结构。 POP结构包括第一裸片，第二裸片和光成像电介质（PID）层。 PID层设置在第一管芯和第二管芯之间。 POP结构还包括从第一管芯通过PID层到第二管芯的第一导电路径。 第一导电路径直接在第一管芯和第二管芯之间直接延伸通过PID层的第一区域。 POP结构还包括从第一管芯通过PID层到第二管芯的第二导电路径。 第二导电路径的特定部分垂直于第一导电路径并且不直接在第一管芯和第二管芯之间延伸穿过PID层的第二区域。

公开(公告)号：US20160133571A1

公开(公告)日：2016-05-12

申请号：US14535966

申请日：2014-11-07

Applicant: QUALCOMM Incorporated

Inventor： Jae Sik Lee ,  Hong Bok We ,  Dong Wook Kim ,  Shiqun Gu

IPC: H01L23/538 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5389 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L23/3107 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/19 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92124 ,  H01L2924/15192 ,  H01L2924/18161 ,  H01L2924/18162

Abstract: Some novel features pertain to an integrated device package that includes an encapsulation portion and a redistribution portion. The encapsulation portion includes a first die, a first set of vias coupled to the first die, a second die, a second set of vias coupled to the second die, a bridge, and an encapsulation layer. The bridge is configured to provide an electrical path between the first die and the second die. The bridge is coupled to the first die through the first set of vias. The bridge is further coupled to the second die through the second set of vias. The encapsulation layer at least partially encapsulates the first die, the second die, the bridge, the first set of vias, and the second set of vias. The redistribution portion is coupled to the encapsulation portion. The redistribution portion includes a set of redistribution interconnects, and at least one dielectric layer.

Abstract translation: 一些新颖的特征涉及包括封装部分和再分配部分的集成器件封装。 封装部分包括第一管芯，耦合到第一管芯的第一组通孔，第二管芯，耦合到第二管芯的第二组通孔，桥接器和封装层。 桥被配置为在第一管芯和第二管芯之间提供电路径。 桥通过第一组通孔耦合到第一个模具。 桥通过第二组通孔进一步耦合到第二管芯。 封装层至少部分地封装第一管芯，第二管芯，桥接器，第一组通孔和第二组通孔。 再分配部分耦合到封装部分。 再分配部分包括一组再分布互连和至少一个电介质层。

公开(公告)号：US09230936B2

公开(公告)日：2016-01-05

申请号：US14196817

申请日：2014-03-04

Applicant: QUALCOMM Incorporated

Inventor： Dong Wook Kim ,  Hong Bok We ,  Jae Sik Lee ,  Shiqun Gu

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/25 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/24137 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1815 ,  H01L2924/014

Abstract: Some novel features pertain to an integrated device (e.g., integrated package) that includes a base portion for the integrated device, a first die coupled to a first surface of the base portion, and an underfill between the first die and the base portion. The base portion includes a dielectric layer, and a set of redistribution metal layers. In some implementations, the integrated device further includes an encapsulation material that encapsulates the first die. In some implementations, the integrated device further includes a second die coupled to the first surface of the base portion. In some implementations, the integrated device further includes a set of interconnects on the base portion, the set of interconnects electrically coupling the first die and the second die. In some implementations, the first die includes a first set of interconnect pillars and the second die includes a second set of interconnect pillars.

Abstract translation: 一些新颖的特征涉及一种集成器件（例如，集成封装），其包括用于集成器件的基座部分，耦合到基部部分的第一表面的第一管芯以及第一管芯和基部之间的底部填充。 基部包括电介质层和一组再分布金属层。 在一些实施方案中，集成器件还包括封装第一裸片的封装材料。 在一些实施方案中，集成装置还包括耦合到基部的第一表面的第二模具。 在一些实施方案中，集成器件还包括在基部上的一组互连，该组互连电耦合第一管芯和第二管芯。 在一些实施方案中，第一管芯包括第一组互连柱，并且第二管芯包括第二组互连柱。

公开(公告)号：US09209131B2

公开(公告)日：2015-12-08

申请号：US14160448

申请日：2014-01-21

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Ryan David Lane ,  Urmi Ray

IPC: H01L23/485 ,  H01L23/522 ,  H01L21/768 ,  H01L49/02 ,  H01L23/538

CPC classification number: H01L23/5227 ,  H01L21/76838 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/19 ,  H01L28/10 ,  H01L2224/04105 ,  H01L2224/11 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some features pertain to an integrated device that includes a substrate, several metal layers coupled to the substrate, several dielectric layers coupled to the substrate, a first metal redistribution layer coupled to one of the metal layers, and a second metal redistribution layer coupled to the first metal redistribution layer. The first and second metal redistribution layers are configured to operate as a toroid inductor in the integrated device. In some implementations, the integrated device also includes a third metal redistribution layer. The third metal redistribution layer is coupled to the first and second metal redistribution layers. The third metal redistribution layer is a via. In some implementations, the first, second, and third metal redistribution layers are configured to operate as a toroid inductor in the integrated device. In some implementations, the first, second, and third redistribution layers form a set of windings for the toroid inductor.

Abstract translation: 一些特征涉及集成器件，其包括衬底，耦合到衬底的几个金属层，耦合到衬底的几个电介质层，耦合到金属层中的一个的第一金属再分布层，以及耦合到衬底的第二金属再分配层 第一金属再分配层。 第一和第二金属再分布层被配置为在集成器件中作为环形电感器工作。 在一些实施方案中，集成器件还包括第三金属再分配层。 第三金属再分布层耦合到第一和第二金属再分配层。 第三金属再分配层是通孔。 在一些实施方案中，第一，第二和第三金属再分配层被配置为在集成器件中作为环形电感器工作。 在一些实施方案中，第一，第二和第三再分配层形成用于环形电感器的一组绕组。

公开(公告)号：US09153461B2

公开(公告)日：2015-10-06

申请号：US14578330

申请日：2014-12-19

Applicant: QUALCOMM Incorporated

Inventor： Brian M. Henderson ,  Shiqun Gu

IPC: H01L21/50 ,  H01L25/18 ,  H01L25/065 ,  H01L23/498 ,  H01L23/48 ,  H01L23/525 ,  H01L23/00

CPC classification number: H01L21/50 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/525 ,  H01L24/17 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2224/13099

Abstract: A semiconductor device includes a die coupled to a substrate, a first memory device coupled to a surface of the die opposite the substrate and a coupling device coupled between the surface of the die opposite the substrate and a second memory device such that the second memory device at least partially overlaps the first memory device. Also disclosed is method of mounting first and second memory devices on a die in an at least partially overlapping manner.

公开(公告)号：US20150214127A1

公开(公告)日：2015-07-30

申请号：US14162969

申请日：2014-01-24

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Ratibor Radojcic ,  Dong Wook Kim

IPC: H01L23/367 ,  H01L23/544 ,  H01L23/00

CPC classification number: H01L23/367 ,  H01L23/13 ,  H01L23/3677 ,  H01L23/473 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L24/32 ,  H01L24/83 ,  H01L2223/54426 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/92244 ,  H01L2924/1015 ,  H01L2924/12042 ,  H01L2924/15151 ,  H01L2924/15156 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/00

Abstract: Some features pertain to an integrated device that includes a substrate. The substrate includes a first cavity (e.g., trench). The first cavity includes a first edge that is non-vertical. The first cavity is configured to align a die towards a center of the first cavity when the die is placed off-center of the first cavity. The integrated device also includes a first die positioned in the first cavity. The integrated device further includes a redistribution portion coupled to the first die. In some implementations, the first edge is a first wall of the first cavity. In some implementations, the first cavity includes a first opening and a first base portion. The first opening of the first cavity is greater than the first base portion of the first cavity.

Abstract translation: 一些特征涉及包括基板的集成装置。 衬底包括第一腔（例如沟槽）。 第一腔包括非垂直的第一边缘。 第一腔被配置成当模具被放置在第一腔体的中心以下时将模具朝着第一空腔的中心对准。 集成装置还包括位于第一腔中的第一模具。 集成器件还包括耦合到第一管芯的再分配部分。 在一些实施方式中，第一边缘是第一腔的第一壁。 在一些实施方式中，第一腔包括第一开口和第一基部。 第一腔的第一开口大于第一腔的第一基部。