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    Method for stabilizing high pressure oxidation of a semiconductor device
    42.
    发明申请
    Method for stabilizing high pressure oxidation of a semiconductor device 失效
    稳定半导体器件的高压氧化的方法

    公开(公告)号：US20060035473A1

    公开(公告)日：2006-02-16

    申请号：US11251973

    申请日：2005-10-17

    申请人： F. Gealy ,  Dave Chapek ,  Scott DeBoer ,  Husam Al-Shareef ,  Randhir Thakur

    发明人： F. Gealy ,  Dave Chapek ,  Scott DeBoer ,  Husam Al-Shareef ,  Randhir Thakur

    IPC分类号： H01L21/31

    CPC分类号： H01L21/28202 ,  C30B33/005 ,  H01L21/02183 ,  H01L21/02197 ,  H01L21/02271 ,  H01L21/31662 ,  H01L29/518 ,  Y10S438/903

    摘要： A method and apparatus for preventing N2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace are disclosed. The method and apparatus utilize a catalyst to catalytically disassociate N2O as it enters the high pressure oxidation furnace. This catalyst is used in an environment of between five atmospheres and 25 atmospheres N2O and a temperature range of 600° to 750° C., which are the conditions that lead to the N2O going super critical. By preventing the N2O from becoming super critical, the reaction is controlled that prevents both temperature and pressure spikes. The catalyst can be selected from the group of noble transition metals and their oxides. This group can comprise palladium, platinum, iridium, rhodium, nickel, silver, and gold.

    摘要翻译： 公开了一种在高压氧化炉内的高压氧化阶段防止N 2 O变得超临界的方法和装置。 该方法和装置利用催化剂在进入高压氧化炉时催化分解N 2 O 2。 该催化剂在五个大气压和25个大气压N 2 O 2的温度范围和600℃至750℃的温度范围内使用，这是导致N 2 O超级关键。 通过防止N 2 O 2变得超临界，控制反应以防止温度和压力尖峰。 催化剂可以选自贵金属过渡金属及其氧化物。 该组可以包括钯，铂，铱，铑，镍，银和金。

    Process for growing a dielectric layer on a silicon-containing surface using a mixture of N2O and O3
    44.
    发明申请
    Process for growing a dielectric layer on a silicon-containing surface using a mixture of N2O and O3 有权
    使用N2O和O3的混合物在含硅表面上生长电介质层的方法

    公开(公告)号：US20050153569A1

    公开(公告)日：2005-07-14

    申请号：US11075187

    申请日：2005-03-08

    申请人： Gurtej Sandhu ,  Randhir Thakur

    发明人： Gurtej Sandhu ,  Randhir Thakur

    IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L29/51 ,  H01L21/31 ,  C23C14/10 ,  H01L21/336 ,  H01L21/469

    CPC分类号： H01L21/28202 ,  H01L21/0214 ,  H01L21/02249 ,  H01L21/02255 ,  H01L21/28185 ,  H01L21/28211 ,  H01L21/31662 ,  H01L21/32105 ,  H01L29/518

    摘要： This invention is embodied in an improved process for growing high-quality silicon dioxide layers on silicon by subjecting it to a gaseous mixture of nitrous oxide (N2O) and ozone (O3). The presence of O3 in the oxidizing ambiance greatly enhances the oxidation rate compared to an ambiance in which N2O is the only oxidizing agent. In addition to enhancing the oxidation rate of silicon, it is hypothesized that the presence of O3 interferes with the growth of a thin silicon oxynitride layer near the interface of the silicon dioxide layer and the unreacted silicon surface which makes oxidation in the presence of N2O alone virtually self-limiting. The presence of O3 in the oxidizing ambiance does not impair oxide reliability, as is the case when silicon is oxidized with N2O in the presence of a strong, fluorine-containing oxidizing agent such as NF3 or SF6.

    摘要翻译： 本发明体现在用于通过使其经受一氧化二氮（N 2 O 2 O）和臭氧（O 3 O 3）的气体混合物在硅上生长高质量二氧化硅层的改进方法， SUB>）。 氧化气氛中O 3 3的存在与其中N 2 O 2是唯一的氧化剂的环境相比，大大地提高了氧化速率。 除了提高硅的氧化速率之外，假设O 3 3的存在妨碍了二氧化硅层和未反应的硅表面界面附近的薄氧氮化硅层的生长， 在N 2 O 2存在下进行氧化，实际上是自限制的。 氧化气氛中的O 3 3的存在不会损害氧化物的可靠性，如在强的氟化物存在下用N 2 O 2氧化硅的情况， 含有氧化剂如NF 3或SF 6。

    Apparatus for stabilizing high pressure oxidation of a semiconductor device
    45.
    发明申请
    Apparatus for stabilizing high pressure oxidation of a semiconductor device 有权
    用于稳定半导体器件的高压氧化的装置

    公开(公告)号：US20050028936A1

    公开(公告)日：2005-02-10

    申请号：US10933890

    申请日：2004-09-02

    申请人： F. Gealy ,  Dave Chapek ,  Scott DeBoer ,  Husam Al-shareef ,  Randhir Thakur

    发明人： F. Gealy ,  Dave Chapek ,  Scott DeBoer ,  Husam Al-shareef ,  Randhir Thakur

    IPC分类号： C30B33/00 ,  H01L21/316 ,  C23F1/00

    CPC分类号： H01L21/28202 ,  C30B33/005 ,  H01L21/02183 ,  H01L21/02197 ,  H01L21/02271 ,  H01L21/31662 ,  H01L29/518 ,  Y10S438/903

    摘要： A method and apparatus for preventing N2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace are disclosed. The method and apparatus utilize a catalyst to catalytically disassociate N2O as it enters the high pressure oxidation furnace. This catalyst is used in an environment of between five (5) atmospheres to twenty-five (25) atmospheres N20 and a temperature range of 600° to 750° C., which are the conditions that lead to the N2O going super critical. By preventing the N2O from becoming super critical, the reaction is controlled that prevents both temperature and pressure spikes. The catalyst can be selected from the group of noble transition metals and their oxides. This group can comprise palladium, platinum, iridium, rhodium, nickel, silver, and gold.

    摘要翻译： 公开了一种在高压氧化炉内高压氧化阶段防止N2O变得超临界的方法和装置。 该方法和装置利用催化剂在进入高压氧化炉时催化分解N2O。 该催化剂用于在五（5）大气压至二十五（25）个大气压二氧化氮和600℃至750℃的温度范围的环境中，这是导致N2O变得超临界的条件。 通过防止N2O变得超临界，可以控制反应，防止温度和压力尖峰。 催化剂可以选自贵金属过渡金属及其氧化物。 该组可以包括钯，铂，铱，铑，镍，银和金。

    DRAM capacitor formulation using a double-sided electrode
    47.
    发明授权
    DRAM capacitor formulation using a double-sided electrode 失效
    DRAM电容器配方采用双面电极

    公开(公告)号：US06737696B1

    公开(公告)日：2004-05-18

    申请号：US09089445

    申请日：1998-06-03

    申请人： Scott J. DeBoer ,  Husam Al-Shareef ,  Randhir Thakur

    发明人： Scott J. DeBoer ,  Husam Al-Shareef ,  Randhir Thakur

    IPC分类号： H01L27108

    CPC分类号： H01L27/10852 ,  H01L21/31604 ,  H01L27/10811 ,  H01L27/10888 ,  H01L28/55 ,  H01L28/91

    摘要： A capacitor having a double sided electrode for enhanced capacitance. In one embodiment, the double sided electrode capacitor is a stacked container capacitor used in a dynamic random access memory circuit. The double sided electrode is preferably formed of a conductive metal, provided that an oxide of the metal is conductive. The double sided electrode capacitor provides a capacitor that has high storage capacitance which provides an increased efficiency for a cell without an increase in the size of the cell.

    摘要翻译： 具有用于增强电容的双面电极的电容器。 在一个实施例中，双面电极电容器是用于动态随机存取存储器电路中的层叠容器电容器。 双面电极优选由导电金属形成，只要金属的氧化物是导电的。 双面电极电容器提供具有高存储电容的电容器，其在不增加电池尺寸的情况下为电池提供增加的效率。

    Shallow doped junctions with a variable profile gradation of dopants
    48.
    发明授权
    Shallow doped junctions with a variable profile gradation of dopants 失效
    具有可变轮廓层次的掺杂剂的浅掺杂结

    公开(公告)号：US06717211B2

    公开(公告)日：2004-04-06

    申请号：US09981549

    申请日：2001-10-17

    申请人： Fernando Gonzalez ,  Randhir Thakur

    发明人： Fernando Gonzalez ,  Randhir Thakur

    IPC分类号： H01L2976

    CPC分类号： H01L29/6659 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/2652 ,  H01L29/66575 ,  H01L29/7833 ,  H01L29/7836 ,  Y10S257/90

    摘要： An electrical device including a shallow junction with a variable concentration profile gradation of dopants. The junction is suitable for forming source and drain regions in MOS transistors, especially where a contact or interconnect is intended to engage the source and drain regions. The variable concentration profile gradation of dopants helps to maintain proper threshold voltage levels and reduces reverse bias current leakage. The electrical device includes a semiconductor substrate having a top surface, a gate region overlapping a portion of the semiconductor substrate, and a source/drain region disposed within the semiconductor substrate. The source/drain region includes an inner portion and an outer portion, wherein the inner portion extends from the top surface of the semiconductor substrate to a bottom periphery and does not underlap the gate region, and the outer portion extends from the bottom periphery of the inner portion and underlaps the gate region. An electrical insulation layer is situated upon the gate region and overlaps the source/drain region.

    摘要翻译： 包括具有可变浓度分布层级的掺杂剂的浅结的电气装置。 该结适用于在MOS晶体管中形成源极和漏极区域，特别是在接触或互连用于接合源极和漏极区域的情况下。 掺杂剂的可变浓度分布层次有助于保持适当的阈值电压电平并减少反向偏置电流泄漏。 电气装置包括具有顶表面，与半导体衬底的一部分重叠的栅极区域和设置在半导体衬底内的源极/漏极区域的半导体衬底。 源极/漏极区域包括内部部分和外部部分，其中内部部分从半导体衬底的顶表面延伸到底部周边，并且不会使栅极区域下凹，并且外部部分从底部周边延伸 内部部分并且使栅极区域重叠。 电绝缘层位于栅极区上并与源极/漏极区重叠。