公开(公告)号：US20050258452A1

公开(公告)日：2005-11-24

申请号：US11108729

申请日：2005-04-19

申请人： Satoru Konishi ,  Tsuneo Endo ,  Hirokazu Nakajima ,  Yasunari Umemoto ,  Satoshi Sasaki ,  Chushiro Kusano ,  Yoshinori Imamura ,  Atsushi Kurokawa

发明人： Satoru Konishi ,  Tsuneo Endo ,  Hirokazu Nakajima ,  Yasunari Umemoto ,  Satoshi Sasaki ,  Chushiro Kusano ,  Yoshinori Imamura ,  Atsushi Kurokawa

IPC分类号： H01L21/28 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/84 ,  H01L23/34 ,  H01L23/482 ,  H01L23/498 ,  H01L25/065 ,  H01L25/07 ,  H01L25/16 ,  H01L25/18 ,  H01L27/082 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/737 ,  H01L29/739 ,  H01L29/78

CPC分类号： H01L29/4933 ,  H01L21/84 ,  H01L23/4824 ,  H01L23/49844 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/16 ,  H01L29/456 ,  H01L29/7835 ,  H01L2224/1403 ,  H01L2224/16235 ,  H01L2224/1703 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has an external wiring for GND formed over an underside surface of a wiring substrate. A plurality of via holes connecting to the external wiring for GND are formed to penetrate the wiring substrate. A first semiconductor chip of high power consumption, including HBTs, is mounted over a principal surface of the wiring substrate. The emitter bump electrode of the first semiconductor chip is connected in common with emitter electrodes of a plurality of HBTs formed in the first semiconductor chip. The emitter bump electrode is extended in a direction in which the HBTs line up. The first semiconductor chip is mounted over the wiring substrate so that a plurality of the via holes are connected with the emitter bump electrode. A second semiconductor chip lower in heat dissipation value than the first semiconductor chip is mounted over the first semiconductor chip.

摘要翻译： 半导体器件具有在布线基板的下表面上形成的用于GND的外部布线。 连接到GND的外部配线的多个通孔形成为穿透布线基板。 包括HBT的高功率的第一半导体芯片安装在布线基板的主表面上。 第一半导体芯片的发射极电极与形成在第一半导体芯片中的多个HBT的发射极共同连接。 发射极电极沿HBT排列的方向延伸。 第一半导体芯片安装在布线基板上，使得多个通孔与发射极电极连接。 散热值比第一半导体芯片低的第二半导体芯片安装在第一半导体芯片上。

公开(公告)号：US5381027A

公开(公告)日：1995-01-10

申请号：US134622

申请日：1993-10-12

申请人： Toshiyuki Usagawa ,  Kenji Hiruma ,  Masahiko Kawata ,  Shigeo Goto ,  Katsuhiko Mitani ,  Masao Yamane ,  Susumu Takahashi ,  Tomonori Tanoue ,  Yoshinori Imamura

发明人： Toshiyuki Usagawa ,  Kenji Hiruma ,  Masahiko Kawata ,  Shigeo Goto ,  Katsuhiko Mitani ,  Masao Yamane ,  Susumu Takahashi ,  Tomonori Tanoue ,  Yoshinori Imamura

IPC分类号： H01L21/18 ,  H01L21/285 ,  H01L21/331 ,  H01L21/335 ,  H01L27/06 ,  H01L29/737 ,  H01L29/778 ,  H01L29/804 ,  H01L29/784

CPC分类号： H01L29/66318 ,  H01L21/182 ,  H01L21/28587 ,  H01L27/0605 ,  H01L29/66462 ,  H01L29/7373 ,  H01L29/7787

摘要： This invention discloses a heterojunction type field effect transistor such as 2DEG-FET and a heterojunction type bipolar transistor such as 2DEG-HBT. The former is fabricated by applying to the formation of its source and drain regions a technique which causes the disorder of the heterojunction by intoduction of an impurity such as by ion implantation or a technique which causes the disorder of the heterojunction by forming a film made of at least one kind of material selected from insulators, metals and semiconductors which have a different linear coefficient of thermal expansion from that of the material of a semiconductor substrate on the heterojunction semiconductor region which is to be disordered. The latter is fabricated by applying either of the techniques described above to a base ohmic contact region. These semiconductor devices can reduce the source-gate resistance and the parasitic base resistance. The invention discloses also the structure of the ohmic contact layer which has a trench on the surface thereof and is particularly effective for reducing the source-gate parasitic resistance.

摘要翻译： 本发明公开了一种异质结型场效应晶体管，例如2DEG-FET和异质结型双极晶体管，例如2DEG-HBT。 前者通过应用于其源极和漏极区域的形成来制造通过诸如通过离子注入引起杂质的异质结的紊乱或通过形成由 选自绝缘体，金属和半导体的至少一种材料，其具有不同于待混杂的异质结半导体区域上的半导体衬底的材料的线性热膨胀系数。 后者通过将上述技术中的任一种应用于基极欧姆接触区域来制造。 这些半导体器件可以降低源极栅极电阻和寄生基极电阻。 本发明还公开了欧姆接触层的结构，其在其表面上具有沟槽，并且对于减小源极寄生电阻特别有效。

公开(公告)号：US4902635A

公开(公告)日：1990-02-20

申请号：US175704

申请日：1988-03-31

申请人： Yoshinori Imamura ,  Masaru Miyazaki ,  Akihisa Terano ,  Nobutoshi Matsunaga ,  Hiroshi Yanazawa

发明人： Yoshinori Imamura ,  Masaru Miyazaki ,  Akihisa Terano ,  Nobutoshi Matsunaga ,  Hiroshi Yanazawa

IPC分类号： H01L21/338 ,  H01L21/768 ,  H01L21/8252 ,  H01L23/532 ,  H01L29/417 ,  H01L29/423 ,  H01L29/812

CPC分类号： H01L23/5329 ,  H01L21/7688 ,  H01L21/8252 ,  H01L29/41775 ,  H01L29/42316 ,  H01L2924/0002

摘要： This invention is related to the method for production of semiconductor devices suitable for increasing the integration density of semiconductor integrated circuits, especially GaAs semiconductor IC devices.This invention uses no third wiring metal, contact hole or through hole for connection between the Schottky junction and ohmic electrodes formed on the GaAs semiconductor substrate required in the conventional technology, but provides the method for direct connection between the two electrodes stated above by means of vapor deposition, ion implantation, sputtering, CVD, plasma CVD, dry etching and wet etching.Since the application of this invention enables the two electrodes stated above to be directly connected with high yield, the element area at the connecting portion can be reduced to less than half as compared with the same required in the conventional method, the total element area can be reduced greatly.

摘要翻译： 本发明涉及适用于提高半导体集成电路，尤其是GaAs半导体IC器件的集成密度的半导体器件的制造方法。 本发明不使用在传统技术中所需的GaAs半导体衬底上形成的肖特基结和欧姆电极之间的第三布线金属，接触孔或通孔，而是提供了通过以下方式直接连接在上述两个电极之间的方法： 气相沉积，离子注入，溅射，CVD，等离子体CVD，干蚀刻和湿蚀刻。 由于本发明的应用使得上述两个电极能够以高产率直接连接，所以连接部分的元件面积可以比常规方法所需的量减少到小于一半，总元件面积可以 大大减少

公开(公告)号：US07723753B2

公开(公告)日：2010-05-25

申请号：US11962169

申请日：2007-12-21

申请人： Kenji Sasaki ,  Ikuro Akazawa ,  Yoshinori Imamura ,  Atsushi Kurokawa ,  Tatsuhiko Ikeda ,  Hiroshi Inagawa ,  Yasunari Umemoto ,  Isao Obu

发明人： Kenji Sasaki ,  Ikuro Akazawa ,  Yoshinori Imamura ,  Atsushi Kurokawa ,  Tatsuhiko Ikeda ,  Hiroshi Inagawa ,  Yasunari Umemoto ,  Isao Obu

IPC分类号： H01L27/082 ,  H01L21/331

CPC分类号： H01L21/8252 ,  H01L23/481 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L27/0605 ,  H01L29/0619 ,  H01L29/7371 ,  H01L29/7811 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/451 ,  H01L2224/45117 ,  H01L2224/45144 ,  H01L2224/45155 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/05042 ,  H01L2924/10158 ,  H01L2924/10329 ,  H01L2924/10336 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/01032 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： In a GaAs substrate as a semi-insulating substrate, a heterojunction bipolar transistor (HBT) is formed in an element formation region, while an isolation region is formed in an insulating region. The isolation region formed in the insulating region is formed by introducing helium into the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT. In an outer peripheral region, a conductive layer is formed to be exposed from protective films and coupled to a back surface electrode. Because a GND potential is supplied to the back surface electrode, the conductive layer is fixed to the GND potential. The conductive layer is formed of the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT.

摘要翻译： 在作为半绝缘基板的GaAs衬底中，在元件形成区域中形成异质结双极晶体管（HBT），而在绝缘区域中形成隔离区域。 通过将氦引入与HBT的副集电极半导体层和集电体半导体层相同的半导体层中而形成在绝缘区域中的隔离区域。 在外围区域中，形成导电层以从保护膜露出并耦合到背面电极。 由于将GND​​电位提供给背面电极，所以导电层固定为GND电位。 导电层由与HBT的副集电极半导体层和集电极半导体层相同的半导体层形成。

公开(公告)号：US20100098476A1

公开(公告)日：2010-04-22

申请号：US12528724

申请日：2008-02-08

申请人： Yoshinori Imamura ,  Nobuo Sekine ,  Masashi Ando

发明人： Yoshinori Imamura ,  Nobuo Sekine ,  Masashi Ando

IPC分类号： B43K29/00

CPC分类号： B43K5/16 ,  B43K1/086 ,  B43K7/02 ,  B43K7/08 ,  B43K7/10 ,  B43K7/12 ,  B43K23/12 ,  B43K24/06 ,  B43K24/08 ,  B43K24/082 ,  B43K24/12 ,  B43K27/12 ,  B43K29/02 ,  C09D11/16 ,  C09D11/50

摘要： There is provided a thermochromic writing instrument containing a thermochromic ink, which is capable of easily changing color of the handwriting of thermochromic ink by rubbing and also being quickly brought into a writing-capable state (pen-tip-projected state) or a stored state (pen-tip-retracted state) even when the user can use only one hand.The thermochromic writing instrument containing a thermochromic ink, wherein a writing body 8 is accommodated in a barrel 2 movably in a longitudinal direction, an operation portion 5 is provided on the outer surface of the barrel 2, a pen tip 81 of the writing body 8 is constituted so as to be projectable/retractable from/into a front-end hole 31 of the barrel 2 by operating the operation portion 5, the thermochromic ink 83 is contained in the inside of the writing body 8, the pen tip 81 capable of ejecting the thermochromic ink 83 is provided at the front end of the writing tool, and a friction portion 4 capable of thermally changing the color of the handwriting of the thermochromic ink 83 by the frictional heat generated when the handwriting is rubbed with the friction portion 4 is provided on the outer surface of the barrel 2.

摘要翻译： 提供了一种含有热变色油墨的热变色书写工具，其能够通过摩擦容易地改变热变色油墨的手写体的颜色，并且还快速进入写入状态（笔尖投影状态）或存储状态 （笔尖缩回状态），即使用户只能使用一只手。 包含热变色油墨的热变色书写工具，其中书写体8容纳在沿纵向可移动的筒体2中，操作部分5设置在筒体2的外表面上，书写体8的笔尖81 通过操作操作部5，能够使其从筒体2的前端孔31突出地伸缩，热敏性油墨83容纳在书写体8的内部，笔尖81能够 喷出热变色油墨83设置在书写工具的前端，以及摩擦部分4，其能够通过摩擦部分4摩擦手写时产生的摩擦热而热变色热变色油墨83的手写的颜色 设置在筒体2的外表面上。

公开(公告)号：US07563021B2

公开(公告)日：2009-07-21

申请号：US10524262

申请日：2003-08-12

申请人： Eiji Ichihara ,  Yoshinori Imamura ,  Takehiko Yamada

发明人： Eiji Ichihara ,  Yoshinori Imamura ,  Takehiko Yamada

IPC分类号： G01K3/00 ,  G01K3/04 ,  G01K1/12

CPC分类号： B60C23/0408 ,  B60C23/20 ,  G01K13/08

摘要： There are provided a process and the like for judging a residual lifetime of a run-flat tire and an end stage of the residual lifetime thereof during continuous running at a run-flat state. The process for judging the residual lifetime of the tire of the invention is characterized in that in a vehicle equipped with a run-flat tire system comprising run-flat tires 2 and detection units 4 each arranged in the respective tire 2 and capable of measuring an atmosphere temperature in at least an interior 3 of the tire 2, when the tire 2 is continuously run at the run-flat state by an extreme lowering of an internal pressure accompanied with the occurrence of puncture or the like, after a limit temperature being statistically an occurrence of trouble is previously set, the atmosphere temperature inside tire of the run-flat tire continuously running at the run-flat state is measured, and a runnable time and/or distance until the run-flat tire results in trouble is predicted by using the atmosphere temperature inside tire measured and data calculated therefrom.

摘要翻译： 提供了一种用于在连续运行中的平坦状态下判断漏气保用轮胎的剩余寿命和剩余寿命的终止阶段的过程等。 用于判断本发明的轮胎的残余寿命的方法的特征在于，在配备有排气轮胎2和检测单元4的排气轮胎系统的车辆中，每个排气轮胎2和检测单元4分别布置在相应的轮胎2中并且能够测量 在轮胎2的至少内部3中的气氛温度，当轮胎2在极限温度为统计学上时，由于伴随着穿刺等的发生的内部压力的极度降低而在平坦状态下连续运行 预先设定故障的发生，测量在平坦状态下持续运行的漏气保用轮胎的轮胎内的气氛温度，直到排气轮胎产生麻烦的运行时间和/或距离由 使用测量的轮胎内部的气氛温度和由此计算的数据。

公开(公告)号：US07511315B2

公开(公告)日：2009-03-31

申请号：US11108729

申请日：2005-04-19

申请人： Satoru Konishi ,  Tsuneo Endo ,  Hirokazu Nakajima ,  Yasunari Umemoto ,  Satoshi Sasaki ,  Chushiro Kusano ,  Yoshinori Imamura ,  Atsushi Kurokawa

发明人： Satoru Konishi ,  Tsuneo Endo ,  Hirokazu Nakajima ,  Yasunari Umemoto ,  Satoshi Sasaki ,  Chushiro Kusano ,  Yoshinori Imamura ,  Atsushi Kurokawa

IPC分类号： H01L21/00 ,  H01L29/34 ,  H01L23/48 ,  H01L21/4763

CPC分类号： H01L29/4933 ,  H01L21/84 ,  H01L23/4824 ,  H01L23/49844 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/16 ,  H01L29/456 ,  H01L29/7835 ,  H01L2224/1403 ,  H01L2224/16235 ,  H01L2224/1703 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has an external wiring for GND formed over an underside surface of a wiring substrate. A plurality of via holes connecting to the external wiring for GND are formed to penetrate the wiring substrate. A first semiconductor chip of high power consumption, including HBTs, is mounted over a principal surface of the wiring substrate. The emitter bump electrode of the first semiconductor chip is connected in common with emitter electrodes of a plurality of HBTs formed in the first semiconductor chip. The emitter bump electrode is extended in a direction in which the HBTs line up. The first semiconductor chip is mounted over the wiring substrate so that a plurality of the via holes are connected with the emitter bump electrode. A second semiconductor chip lower in heat dissipation value than the first semiconductor chip is mounted over the first semiconductor chip.

摘要翻译： 半导体器件具有在布线基板的下表面上形成的用于GND的外部布线。 连接到GND的外部配线的多个通孔形成为穿透布线基板。 包括HBT的高功率的第一半导体芯片安装在布线基板的主表面上。 第一半导体芯片的发射极电极与形成在第一半导体芯片中的多个HBT的发射极共同连接。 发射极电极沿HBT排列的方向延伸。 第一半导体芯片安装在布线基板上，使得多个通孔与发射极电极连接。 散热值比第一半导体芯片低的第二半导体芯片安装在第一半导体芯片上。

公开(公告)号：US20080224174A1

公开(公告)日：2008-09-18

申请号：US11962169

申请日：2007-12-21

申请人： Kenji SASAKI ,  Ikuro Akazawa ,  Yoshinori Imamura ,  Atsushi Kurokawa ,  Tatsuhiko Ikeda ,  Hiroshi Inagawa ,  Yasunari Umemoto ,  Isao Obu

发明人： Kenji SASAKI ,  Ikuro Akazawa ,  Yoshinori Imamura ,  Atsushi Kurokawa ,  Tatsuhiko Ikeda ,  Hiroshi Inagawa ,  Yasunari Umemoto ,  Isao Obu

IPC分类号： H01L27/082 ,  H01L21/331

CPC分类号： H01L21/8252 ,  H01L23/481 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L27/0605 ,  H01L29/0619 ,  H01L29/7371 ,  H01L29/7811 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/451 ,  H01L2224/45117 ,  H01L2224/45144 ,  H01L2224/45155 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/05042 ,  H01L2924/10158 ,  H01L2924/10329 ,  H01L2924/10336 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/01032 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A technology which allows an improvement in the moisture resistance of a semiconductor device is provided. In a GaAs substrate as a semi-insulating substrate, a HBT is formed in an element formation region, while an isolation region is formed in an insulating region. The isolation region formed in the insulating region is formed by introducing helium into the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT. In an outer peripheral region, a conductive layer is formed to be exposed from protective films and coupled to a back surface electrode. Because a GND potential is supplied to the back surface electrode, the conductive layer is fixed to the GND potential. The conductive layer is formed of the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT.

摘要翻译： 提供了允许提高半导体器件的耐湿性的技术。 在作为半绝缘基板的GaAs衬底中，在元件形成区域中形成HBT，而在绝缘区域中形成隔离区域。 形成在绝缘区域中的隔离区域通过将氦引入与HBT的子集电极半导体层和集电极半导体层相同的半导体层中而形成。 在外围区域中，形成导电层以从保护膜露出并耦合到背面电极。 由于将GND​​电位提供给背面电极，所以导电层固定为GND电位。 导电层由与HBT的副集电极半导体层和集电极半导体层相同的半导体层形成。

公开(公告)号：US07029938B2

公开(公告)日：2006-04-18

申请号：US10809525

申请日：2004-03-26

申请人： Atsushi Kurokawa ,  Hiroshi Inagawa ,  Toshiaki Kitahara ,  Yoshinori Imamura

发明人： Atsushi Kurokawa ,  Hiroshi Inagawa ,  Toshiaki Kitahara ,  Yoshinori Imamura

IPC分类号： H01L21/00 ,  H01L21/8238

CPC分类号： H01L29/66318 ,  H01L29/0657 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/7371

摘要： Upon formation of a collector electrode around a base mesa by the lift-off method, a resist film is formed over connection portions between the outer periphery of a region OA1 and a region in which the base mesa is formed, followed by successive formation of gold germanium, nickel and Au in this order over the entire surface of a substrate, so that the resulting stacked film will not become an isolated pattern. Thus, the stacked film over the base mesa is connected to a stacked film at the outer periphery of the region OA1, facilitating peeling of the stacked film over the base mesa. Generation of side etching upon formation of a via hole extending from the back side of the substrate to a backside via electrode is reduced by forming the backside via electrode using a material which hardly reacts with an n-type GaAs layer or n-type InGaAs layer.

摘要翻译： 通过剥离法在集电体周围形成集电体电极时，在区域OA1的外周与形成有基台面的区域之间的连接部分上形成抗蚀剂膜，接着形成 金，锗，金等，从而使得所得到的层叠膜不会成为隔离图案。 因此，基底台面上的层叠膜在区域OA1的外周与层叠膜连接，有利于层叠膜在基台面上的剥离。 通过使用几乎不与n型GaAs层或n型InGaAs层反应的材料形成背面通孔电极来减少形成从基板的背面延伸到背面通孔电极的通孔形成侧面蚀刻 。

公开(公告)号：US20060032762A1

公开(公告)日：2006-02-16

申请号：US11257060

申请日：2005-10-25

申请人： Atsushi Kurokawa ,  Hiroshi Inagawa ,  Toshiaki Kitahara ,  Yoshinori Imamura

发明人： Atsushi Kurokawa ,  Hiroshi Inagawa ,  Toshiaki Kitahara ,  Yoshinori Imamura

IPC分类号： B65D75/00

CPC分类号： H01L29/66318 ,  H01L29/0657 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/7371

摘要： Provided is a technique of improving the properties of a bipolar transistor. Described specifically, upon formation of a collector electrode around a base mesa by the lift-off method, a resist film is formed over connection portions between the outer periphery of a region OA1 and a region in which the base mesa 4a is formed, followed by successive formation of gold germanium (AuGe), nickel (Ni) and Au in the order of mention over the entire surface of a substrate so that the stacked film of them will not become an isolated pattern. As a result, the stacked film over the base mesa 4a is connected to a stacked film at the outer periphery of the region OA1, facilitating peeling of the stacked film over the base mesa 4a. In addition, generation of side etching upon formation of a via hole extending from the back side of the substrate to a backside via electrode is reduced by forming the backside via electrode using a material such as WSi which hardly reacts with an n type GaAs layer or n type InGaAs layer.

摘要翻译： 提供了改进双极晶体管的性质的技术。 具体地说，通过剥离法在基台周围形成集电极时，在区域OA1的外周与形成有基台面4a的区域之间的连接部分上形成抗蚀剂膜， 随后在衬底的整个表面上依次形成金锗（AuGe），镍（Ni）和Au，使得它们的堆叠膜不会变成隔离图案。 结果，基底台面4a上的层叠膜在区域OA1的外周与层叠膜连接，有利于层叠膜在基台面4a上的剥离。 此外，通过使用几乎不与n型GaAs层反应的诸如WSi的材料形成背面通孔电极来减少形成从基板的背面延伸到背面通孔电极的通孔形成侧面蚀刻，或 n型InGaAs层。