公开(公告)号：US11869938B2

公开(公告)日：2024-01-09

申请号：US17516192

申请日：2021-11-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hae Geon Jung ,  Dong Kwon Kim ,  Cheol Kim

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/08

CPC classification number: H01L29/0665 ,  H01L29/0847 ,  H01L29/4236

Abstract: A semiconductor device includes a substrate, a first active pattern that includes a first side wall and a second side wall opposite to the first side wall in a second horizontal direction, a first insulating structure in a first trench extending in the first horizontal direction on the first side wall of the first active pattern, a second insulating structure in a second trench extending in the first horizontal direction on the second side of the first active pattern, and includes a first insulating layer on side walls and a bottom surface of the second trench, and a second insulating layer in the second trench on the first insulating layer, a gate-cut extending in the first horizontal direction on the first insulating structure, and a gate electrode extending in the second horizontal direction on the first active pattern.

公开(公告)号：US20230031542A1

公开(公告)日：2023-02-02

申请号：US17716278

申请日：2022-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Ho Jung ,  Dong Kwon Kim ,  Cheol Kim

IPC: H01L29/06 ,  H01L29/66

Abstract: A semiconductor device includes: a substrate; an active pattern and a field insulating layer surrounding a sidewall of the active pattern on the substrate; first and second gate electrodes on the active pattern and extending in a direction different from that of the active pattern; an interlayer insulating layer surrounding a sidewall of each of the first and second gate electrodes; a gate spacer on opposing sidewalls of each of the first and second gate electrodes that includes a first sidewall and a second sidewall opposite the first sidewall in the first horizontal direction, each of which contacts the interlayer insulating layer; and a first gate cut dividing the second gate electrode into two portions, wherein the first gate cut includes a same material as the gate spacer; and wherein a first width of the first gate cut is smaller than a second width of the gate spacer.

公开(公告)号：US11211450B2

公开(公告)日：2021-12-28

申请号：US16033488

申请日：2018-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-hyun Park ,  Kye-hyun Baek ,  Yong-ho Jeon ,  Cheol Kim ,  Sung-il Park ,  Yun-il Lee ,  Hyung-suk Lee

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66

Abstract: An integrated circuit (IC) device includes a first region and a second region adjacent to each other along a first direction on a substrate, fin patterns in each of the first and second regions extending along a second direction perpendicular to the first direction; gate electrodes extending along the first direction and intersecting the fin patterns; and an isolation region between the first and second regions, a bottom of the isolation region having a non-uniform height relative to a bottom of the substrate.

公开(公告)号：US10395719B2

公开(公告)日：2019-08-27

申请号：US16005880

申请日：2018-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Cheol Kim ,  Kee-Won Kwon ,  Ji-Su Min ,  Rak-Joo Sung ,  Sung-gi Ahn

IPC: G11C11/22 ,  G11C7/12 ,  G11C5/06 ,  G11C15/04

Abstract: A memory device includes a storage circuit, a first driving circuit, and a second driving circuit. The storage circuit stores first data and compares the first data and second data. The first driving circuit selectively drives a matching line to a first logic state, depending on a comparison result of the first data and the second data by the storage circuit. The second driving circuit drives the matching line to a second logic state regardless of the comparison result.

公开(公告)号：US09972538B2

公开(公告)日：2018-05-15

申请号：US15196870

申请日：2016-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheol Kim ,  Dong-Hoon Khang ,  Do-Hyoung Kim ,  Seung-Jin Mun ,  Yong-Joon Choi ,  Seung-Mo Ha

IPC: H01L21/311 ,  H01L21/8234 ,  H01L21/027 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/3105 ,  H01L21/033 ,  H01L21/308 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/02115 ,  H01L21/02271 ,  H01L21/02321 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/0273 ,  H01L21/0275 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31155 ,  H01L29/66795

Abstract: Methods for fabricating a semiconductor device include forming a composite film, forming a rough pattern on the composite film, forming a smooth pattern by subjecting the rough pattern to ion implantation and a plasma treatment, and patterning the composite film using the smooth pattern as a first mask.

公开(公告)号：US09673303B2

公开(公告)日：2017-06-06

申请号：US14820564

申请日：2015-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheol Kim ,  Donghyun Kim ,  Myeongcheol Kim ,  Daeyong Kim ,  Chulsung Kim

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L29/6681 ,  H01L21/31116 ,  H01L21/76897 ,  H01L29/6656

Abstract: Provided are a semiconductor device and a fabrication method thereof. The semiconductor device may include a fin-shaped active pattern and a gate electrode provided on a substrate, first and second spacers provided on a sidewall of the gate electrode, impurity regions provided at both sides of the gate electrode, a contact plug electrically connected to one of the impurity regions, and a third spacer enclosing the contact plug and having a top surface positioned at substantially the same level as a top surface of the contact plug.

公开(公告)号：US09627542B2

公开(公告)日：2017-04-18

申请号：US15144662

申请日：2016-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung-Ho Kwon ,  Cheol Kim ,  Ho-Young Kim ,  Se-Jung Park ,  Myeong-Cheol Kim ,  Bo-Kyeong Kang ,  Bo-Un Yoon ,  Jae-Kwang Choi ,  Si-Young Choi ,  Suk-Hoon Jeong ,  Geum-Jung Seong ,  Hee-Don Jeong ,  Yong-Joon Choi ,  Ji-Eun Han

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/423 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8238 ,  H01L29/49

CPC classification number: H01L29/7853 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

公开(公告)号：US09312181B2

公开(公告)日：2016-04-12

申请号：US14531987

申请日：2014-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Joon Choi ,  Myeongcheol Kim ,  Cheol Kim ,  GeumJung Seong ,  Hak-Sun Lee ,  Haegeon Jung ,  Ji-Eun Han

IPC: H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/762 ,  H01L21/308

CPC classification number: H01L21/823431 ,  H01L21/3081 ,  H01L21/76224 ,  H01L27/0886

Abstract: The disclosure provides semiconductor devices and methods of manufacturing the same. The method includes etching a substrate using a first mask pattern formed on the substrate to form a trench, forming a preliminary device isolation pattern filling the trench and including first and second regions having first thicknesses, forming a second mask pattern on the first region, etching an upper portion of the second region and a portion of the first mask pattern, which are exposed by the second mask pattern, to form a second region having a second thickness smaller than the first thickness, removing the first and second mask patterns, and etching upper portions of the first region and the second region having the second thickness to form a device isolation pattern defining preliminary fin-type active patterns. An electronic device including a semiconductor device and a manufacturing method thereof are also disclosed.

Abstract translation: 本公开提供半导体器件及其制造方法。 该方法包括使用形成在衬底上的第一掩模图案来蚀刻衬底以形成沟槽，形成填充沟槽的初步器件隔离图案，并且包括具有第一厚度的第一和第二区域，在第一区域上形成第二掩模图案，蚀刻 第二区域的上部和第一掩模图案的一部分被第二掩模图案曝光，以形成具有小于第一厚度的第二厚度的第二区域，去除第一和第二掩模图案，以及蚀刻 所述第一区域的上部和所述第二区域具有第二厚度，以形成限定预备鳍型活性图案的器件隔离图案。 还公开了一种包括半导体器件及其制造方法的电子器件。

公开(公告)号：US20150076617A1

公开(公告)日：2015-03-19

申请号：US14548871

申请日：2014-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeong-Cheol Kim ,  Il-Sup Kim ,  Cheol Kim ,  Jong-Chan Shin ,  Jong-Wook Lee ,  Choong-Ho Lee ,  Si-Young Choi ,  Jong-Seo Hong

IPC: H01L27/088 ,  H01L29/16

CPC classification number: H01L27/0886 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L29/16

Abstract: Methods of forming patterns of a semiconductor device are provided. The methods may include forming a hard mask film on a semiconductor substrate. The methods may include forming first and second sacrificial film patterns that are spaced apart from each other on the hard mask film. The methods may include forming a first spacer on opposing sidewalls of the first sacrificial film pattern and a second spacer on opposing sidewalls of the second sacrificial film pattern. The methods may include removing the first and second sacrificial film patterns. The methods may include trimming the second spacer such that a line width of the second spacer becomes smaller than a line width of the first spacer. The methods may include forming first and second hard mask film patterns by etching the hard mask film using the first spacer and the trimmed second spacer as an etch mask.

Abstract translation: 提供了形成半导体器件的图案的方法。 所述方法可以包括在半导体衬底上形成硬掩模膜。 所述方法可以包括形成在硬掩模膜上彼此间隔开的第一和第二牺牲膜图案。 所述方法可以包括在第一牺牲膜图案的相对侧壁上形成第一间隔物，以及在第二牺牲膜图案的相对侧壁上形成第二间隔物。 所述方法可以包括去除第一和第二牺牲膜图案。 所述方法可以包括修整第二间隔物，使得第二间隔物的线宽变得小于第一间隔物的线宽。 所述方法可以包括通过使用第一间隔物和修剪的第二间隔物作为蚀刻掩模蚀刻硬掩模膜来形成第一和第二硬掩模膜图案。

公开(公告)号：US20130215662A1

公开(公告)日：2013-08-22

申请号：US13748773

申请日：2013-01-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Il Lim ,  Cheol Kim ,  Sang-Ho Shin

IPC: G11C17/00

CPC classification number: G11C17/00 ,  G11C17/16 ,  G11C29/785

Abstract: A memory device includes an anti-fuse cell array including a plurality of anti-fuse cells. Each anti-fuse cell includes a first cell transistor connected to a common node, a second cell transistor connected to the common node, and an access transistor connected to the common node. The first cell transistor is configured to store data and the second cell transistor is configured to store data when the first cell transistor has defect data.

Abstract translation: 存储器件包括包括多个反熔丝单元的反熔丝单元阵列。 每个反熔丝单元包括连接到公共节点的第一单元晶体管，连接到公共节点的第二单元晶体管和连接到公共节点的存取晶体管。 第一单元晶体管被配置为存储数据，并且第二单元晶体管被配置为当第一单元晶体管具有缺陷数据时存储数据。