公开(公告)号：US09076881B2

公开(公告)日：2015-07-07

申请号：US14171048

申请日：2014-02-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Hyeok Im ,  Jong-Yeon Kim ,  Tae-Je Cho ,  Un-Byoung Kang

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L24/81 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/11001 ,  H01L2224/13025 ,  H01L2224/13075 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Provided are a bump structure includes a first bump and a second bump, a semiconductor package including the same, and a method of manufacturing the same. The bump structure includes: first bump provided on a connection pad of a substrate, the first bump including a plurality of nano-wires extending from the connection pad and a body connecting end portions of the plurality of nano-wires; and a second bump provided on the body of the first bump.

Abstract translation: 提供一种凸块结构，包括第一凸块和第二凸块，包括该凸块的半导体封装及其制造方法。 凸块结构包括：设置在基板的连接焊盘上的第一凸块，所述第一凸块包括从所述连接焊盘延伸的多个纳米线和连接所述多个纳米线的端部的主体; 以及设置在第一凸块的主体上的第二凸块。

公开(公告)号：US12119306B2

公开(公告)日：2024-10-15

申请号：US18307277

申请日：2023-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il Choi ,  Gyuho Kang ,  Un-Byoung Kang ,  Byeongchan Kim ,  Junyoung Park ,  Jongho Lee ,  Hyunsu Hwang

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5383 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/16225

Abstract: A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.

公开(公告)号：US12040294B2

公开(公告)日：2024-07-16

申请号：US18313560

申请日：2023-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il Choi ,  Un-Byoung Kang ,  Jin Ho An ,  Jongho Lee ,  Jeonggi Jin ,  Atsushi Fujisaki

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0346 ,  H01L2224/03614 ,  H01L2224/0401 ,  H01L2224/05016 ,  H01L2224/0508 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/11849 ,  H01L2224/13026 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155

Abstract: Semiconductor devices are provided. A semiconductor device includes an insulating layer and a conductive element in the insulating layer. The semiconductor device includes a first barrier pattern in contact with a surface of the conductive element and a surface of the insulating layer. The semiconductor device includes a second barrier pattern on the first barrier pattern. Moreover, the semiconductor device includes a metal pattern on the second barrier pattern. Related semiconductor packages are also provided.

公开(公告)号：US11948903B2

公开(公告)日：2024-04-02

申请号：US18119397

申请日：2023-03-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Sick Park ,  Un-Byoung Kang ,  Seon Gyo Kim ,  Joon Ho Jun

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/17 ,  H01L23/481 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/05 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0233 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05078 ,  H01L2224/05562 ,  H01L2224/06158 ,  H01L2224/06182 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/14152 ,  H01L2224/1416 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/17107 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06544

Abstract: A semiconductor package including a first stack; a plurality of TSVs passing through the first stack; a second stack on the first stack and including a second surface facing a first surface of the first stack; a first pad on the first stack and in contact with the TSVs; a second pad on the second stack; a bump connecting the first and second pads; a first redundancy pad on the first surface of the first stack, spaced apart from the first pad, and not in contact with the TSVs; a second redundancy pad on the second surface of the second stack and spaced apart from the second pad; and a redundancy bump connecting the first redundancy pad and the second redundancy pad, wherein the first pad and first redundancy pad are electrically connected to each other, and the second pad and second redundancy pad are electrically connected to each other.

公开(公告)号：US20230275011A1

公开(公告)日：2023-08-31

申请号：US18311621

申请日：2023-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonggi Jin ,  Gyuho Kang ,  Solji Song ,  Un-Byoung Kang ,  Ju-Il Choi

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L23/49838 ,  H01L2224/16227

Abstract: A semiconductor package may include a redistribution substrate having a first surface and a second surface, opposite to each other, a semiconductor chip on the first surface of the redistribution substrate, and a solder pattern on the second surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern coupled to the solder pattern, a first redistribution pattern on the under-bump pattern, the first redistribution pattern including a first via portion and a first wire portion, and a first seed pattern between the under-bump pattern and the first redistribution pattern and on a side surface of the first via portion and a bottom surface of the first wire portion. A bottom surface of the first seed pattern may be at a level lower than a top surface of the under-bump pattern.

公开(公告)号：US11735494B2

公开(公告)日：2023-08-22

申请号：US17408988

申请日：2021-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hee-Jeong Kim ,  Juhyun Lyu ,  Un-Byoung Kang ,  Jongho Lee

IPC: H01L23/373 ,  H01L23/31 ,  H01L23/367

CPC classification number: H01L23/3735 ,  H01L23/3185 ,  H01L23/367

Abstract: Disclosed is a semiconductor package comprising first and second semiconductor structures spaced apart on a first substrate, a heat sink covering the first and second semiconductor structure and the first substrate, and a thermal interface material layer between the heat sink and the first and second semiconductor structures. The first semiconductor structure includes a first sidewall adjacent to the second semiconductor structure and a second sidewall opposite the first sidewall. The thermal interface material layer includes a first segment between the first and second semiconductor structures and a second segment protruding beyond the second sidewall. A first distance from a top surface of the first substrate to a lowest point of a bottom surface of the first segment is less than a second distance from the top surface of the first substrate to a lowest point of a bottom surface of the second segment.

公开(公告)号：US11694996B2

公开(公告)日：2023-07-04

申请号：US17245913

申请日：2021-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuekjae Lee ,  Un-Byoung Kang ,  Sang Cheon Park ,  Jinkyeong Seol ,  Sanghoon Lee

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L24/13 ,  H01L24/20 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/1302 ,  H01L2224/214 ,  H01L2225/06541

Abstract: A semiconductor package is provided. The semiconductor package may include a first semiconductor die, a second semiconductor die stacked on the first semiconductor die, the second semiconductor die having a width smaller than a width of the first semiconductor die, a third semiconductor die stacked on the second semiconductor die, the third semiconductor die having a width smaller than the width of the first semiconductor die, and a mold layer covering side surfaces of the second and third semiconductor dies and a top surface of the first semiconductor die. The second semiconductor die may include a second through via, and the third semiconductor die may include a third conductive pad in contact with the second through via.

公开(公告)号：US20230207532A1

公开(公告)日：2023-06-29

申请号：US18176058

申请日：2023-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonho JUN ,  Un-Byoung Kang ,  Sunkyoung Seo ,  Jongho Lee ,  Young Kun Jee

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/14 ,  H01L24/06 ,  H01L2224/06181 ,  H01L2224/1451 ,  H01L2224/06515 ,  H01L2224/0401 ,  H01L2225/06513

Abstract: A semiconductor package may include first and second substrates, which are vertically stacked, a semiconductor device layer on a bottom surface of the second substrate to face a top surface of the first substrate, upper chip pads and an upper dummy pad on the top surface of the first substrate, penetration electrodes, which each penetrate the first substrate and are connected to separate, respective upper chip pads, lower chip pads on a bottom surface of the semiconductor device layer and electrically connected to separate, respective upper chip pads, and a lower dummy pad on the bottom surface of the semiconductor device layer and electrically isolated from the upper dummy pad. A distance between the upper and lower dummy pads in a horizontal direction that is parallel to the first substrate may be smaller than a diameter of the lower dummy pad.

公开(公告)号：US20230046782A1

公开(公告)日：2023-02-16

申请号：US17700879

申请日：2022-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongho Park ,  Un-Byoung Kang ,  Sechul Park ,  Hyojin Yun ,  Ju-Il Choi ,  Atsushi Fujisaki

IPC: H01L25/065 ,  H01L21/02 ,  H01L21/56 ,  H01L25/00

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a substrate that includes a plurality of vias, a first chip stack on the substrate and including a plurality of first semiconductor chips that are sequentially stacked on the substrate, and a plurality of first non-conductive layers between the substrate and the first chip stack and between neighboring first semiconductor chips. Each of the first non-conductive layers includes first extensions that protrude outwardly from first lateral surfaces of the first semiconductor chips. The more remote the first non-conductive layers are from the substrate, the first extensions protrude a shorter length from the first lateral surfaces of the first semiconductor chips.

公开(公告)号：US11482554B2

公开(公告)日：2022-10-25

申请号：US16898610

申请日：2020-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Un-Byoung Kang ,  Yungcheol Kong ,  Hyunsu Jun ,  Kyoungsei Choi

IPC: H01L27/146 ,  H01L31/0203 ,  H01L23/00 ,  H01L31/024

Abstract: A semiconductor package including a substrate, a memory chip on the substrate, a mold layer on the substrate to cover a side surface of the memory chip, an image sensor chip on the memory chip and the mold layer, and a connection terminal between and electrically connecting the memory chip to the image sensor chip may be provided.