公开(公告)号：US07033923B2

公开(公告)日：2006-04-25

申请号：US11056324

申请日：2005-02-10

申请人： Krishna Seshan

发明人： Krishna Seshan

IPC分类号： H01L21/44

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05551 ,  H01L2224/05557 ,  H01L2224/05578 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15787 ,  H01L2924/30107 ,  H01L2924/00

摘要： The present invention discloses a novel layout and process for a device with segmented BLM for the I/Os. In a first embodiment, each BLM is split into two segments. The segments are close to each other and connected to the same overlying bump. In a second embodiment, each BLM is split into more than two segments. In a third embodiment, each segment is electrically connected to more than one underlying via. In a fourth embodiment, each segment is electrically connected to more than one underlying bond pad.

摘要翻译： 本发明公开了一种用于I / O的具有分段BLM的设备的新颖布局和过程。 在第一实施例中，每个BLM被分成两个段。 这些片段彼此靠近并连接到相同的上覆凸起。 在第二实施例中，每个BLM被分成多于两个段。 在第三实施例中，每个段电连接到多于一个的底层通孔。 在第四实施例中，每个段电连接到多于一个的底层接合焊盘。

公开(公告)号：US20050247931A1

公开(公告)日：2005-11-10

申请号：US11184521

申请日：2005-07-19

申请人： Krishna Seshan

发明人： Krishna Seshan

IPC分类号： H01L23/50 ,  H01L23/538 ,  H01L23/58

CPC分类号： G01R31/31718 ,  G01R31/31723 ,  H01L23/50 ,  H01L23/5382 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01057 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

摘要： Selectable capacitors are used to modify performance characteristics of functional circuit elements of an integrated circuit (IC). In an embodiment, the decoupling capacitors are implemented as additional or alternative mounting pads on a surface of the IC. At least one selectable capacitor is provided for each IC circuit element, such as a logic network, whose operational characteristic(s) is predicted to be and is actually identified as sub-optimal through IC testing, particularly following a process change, a mask shrink, operation of the IC at higher clock frequency, or the like. Expensive redesign is avoided by selectively coupling capacitors into the IC circuit element as needed, under control of selector logic that is responsive to control signals. Methods of operation, as well as application of the apparatus to an electronic assembly and an electronic system, are also described.

摘要翻译： 可选择的电容器用于修改集成电路（IC）的功能电路元件的性能特征。 在一个实施例中，去耦电容器被实现为IC表面上的附加或替代的安装焊盘。 为每个IC电路元件（例如逻辑网络）提供至少一个可选择的电容器，其逻辑网络的操作特性被预测为并通过IC测试被实际识别为次优，特别是在过程变化之后，掩模收缩 ，在较高时钟频率下操作IC等。 在根据控制信号响应的选择器逻辑的控制下，通过选择性地将电容器耦合到IC电路元件中来避免昂贵的重新设计。 还描述了操作方法以及将装置应用于电子组件和电子系统。

公开(公告)号：US06876053B1

公开(公告)日：2005-04-05

申请号：US09374502

申请日：1999-08-13

申请人： Qing Ma ,  Jin Lee ,  Harry Fujimoto ,  Changhong Dai ,  Shiuh-Wuu Lee ,  Travis Eiles ,  Krishna Seshan

发明人： Qing Ma ,  Jin Lee ,  Harry Fujimoto ,  Changhong Dai ,  Shiuh-Wuu Lee ,  Travis Eiles ,  Krishna Seshan

IPC分类号： H01L21/762 ,  H01L29/00 ,  H01L29/76 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7842 ,  H01L21/76224 ,  H01L29/7846 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

摘要： An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.

摘要翻译： 一种用于修改MOS器件的隔离结构配置以诱导或减小MOS器件的有源区上的拉伸和/或压缩应力的装置和方法。 根据本发明的隔离结构构造包括使用低模量和高模量介电材料以及拉伸应力诱导和压应力诱导介电材料，还包括改变隔离深度 用于改变隔离结构构造的结构和方法，例如使用的沟槽深度和隔离材料，以修饰（即，诱发或减少）半导体器件的有源区域上的拉伸和/或压缩应力。

公开(公告)号：US06734544B2

公开(公告)日：2004-05-11

申请号：US10387046

申请日：2003-03-12

申请人： Soupin Yan ,  Krishna Seshan

发明人： Soupin Yan ,  Krishna Seshan

IPC分类号： H01L2348

CPC分类号： H01L24/10 ,  H01L21/563 ,  H01L24/13 ,  H01L24/81 ,  H01L2223/54473 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/14133 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3025 ,  H05K1/0263 ,  H05K3/284 ,  H05K3/3436 ,  H05K2201/0379 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00

摘要： An integrated circuit package is disclosed. According to one embodiment of the present invention an integrated circuit is formed in a die having an edge, and a plurality of non-I/O columns are bonded between a substrate and the die a selected distance from the edge of the die.

摘要翻译： 公开了一种集成电路封装。 根据本发明的一个实施例，在具有边缘的模具中形成集成电路，并且多个非I / O列结合在距离管芯边缘一定距离的衬底和管芯之间。

公开(公告)号：US06377457B1

公开(公告)日：2002-04-23

申请号：US09660859

申请日：2000-09-13

申请人： Krishna Seshan ,  Yves André Volckaert ,  Prosenjit Ghosh

发明人： Krishna Seshan ,  Yves André Volckaert ,  Prosenjit Ghosh

IPC分类号： H05K720

CPC分类号： H05K1/0272 ,  H01L23/467 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electronic assembly is provided. An electronic substrate of the assembly has a plurality of conductive lines to transmit signals, and a cooling opening therethrough. The cooling opening has an inlet to allow fluid into the electronic substrate, a section in the electronic substrate through which the fluid flows from the inlet, and an outlet from which the fluid flows from the section out of the electronic substrate. A semiconductor die of the assembly is mounted to the electronic substrate. The die has an electronic circuit connected to the metal lines so that signals are transmitted between the electronic circuit and the metal lines, operation of the electronic circuit causing heating of the die, heat being transferred from the die to the electronic substrate from where heat is transferred to the fluid flowing through the section.

摘要翻译： 提供电子组件。 组件的电子基板具有多条传输信号的导线和通过其的冷却开口。 冷却开口具有允许流体进入电子基板的入口，电子基板中的流体从入口流过的部分和流体从该部分流出电子基板的出口。 组件的半导体管芯安装到电子基板上。 模具具有连接到金属线的电子电路，使得信号在电子电路和金属线之间传输，电子电路的操作导致模具的加热，热量从模具转移到电子基板，从那里热量是 转移到流经该部分的流体。

公开(公告)号：US6043551A

公开(公告)日：2000-03-28

申请号：US940535

申请日：1997-09-30

申请人： Krishna Seshan

发明人： Krishna Seshan

IPC分类号： H01L23/31 ,  H01L23/58 ,  H01L27/095 ,  H01L31/00

CPC分类号： H01L23/585 ,  H01L23/3171 ,  H01L2924/0002

摘要： An integrated circuit (IC) is provided. The IC includes a silicon substrate and a dielectric layer formed upon the silicon substrate. The IC further includes a terminal metal layer (TML) formed upon the dielectric layer. The dielectric layer and the TML form a die active area. The TML has formed therein a plurality of spaced locking structures. The plurality of space locking structures are electrically isolated therebetween. Each locking structure is formed outside the die active area. The IC further includes a passivation layer adhering to the locking structures.

摘要翻译： 提供集成电路（IC）。 IC包括硅衬底和形成在硅衬底上的电介质层。 IC还包括形成在电介质层上的端子金属层（TML）。 电介质层和TML形成管芯有源区。 TML中形成有多个间隔开的锁定结构。 多个空间锁定结构之间电隔离。 每个锁定结构形成在模具有效区域的外部。 IC还包括粘附到锁定结构的钝化层。

公开(公告)号：US5585663A

公开(公告)日：1996-12-17

申请号：US511565

申请日：1995-08-04

申请人： Raschid J. Bezama ,  Dominic J. Schepis ,  Krishna Seshan

发明人： Raschid J. Bezama ,  Dominic J. Schepis ,  Krishna Seshan

IPC分类号： H01L21/82 ,  H01L23/367 ,  H01L23/525 ,  H01L29/00

CPC分类号： H01L23/5256 ,  H01L23/3672 ,  H01L2924/0002 ,  Y10S438/922

摘要： An electrically programmable fuse buried under quartz and layers of polyimide with a specific structure to enhance its "thermal" capabilities. The fuse is designed to "blow" and cool off quickly so as not to cause damage to areas above and surrounding the fuse. A passivation layer is added above the fuse to act as a heat sink and absorb and redistribute the heat generated from one localized area to a broader and cooler area. The materials used for the fuse and the heat sink are selected to be compatible with both oxide and polyimide personalization schemes. Modeling of the fuse enables optimizing the characteristics of the fuse, particularly to transmit to the surface of the passivation layer the thermal wave created during programming of the fuse.

摘要翻译： 埋在石英下的电可编程熔丝和具有特定结构的聚酰亚胺层，以增强其“热”能力。 保险丝设计为“吹”并快速冷却，以免对保险丝上方和周围的区域造成损坏。 保险丝上方加上钝化层，作为散热片，吸收并重新分配从一个局部区域产生的热量到较宽和较冷的区域。 用于保险丝和散热器的材料被选择为与氧化物和聚酰亚胺个性化方案兼容。 保险丝的建模可以优化保险丝的特性，特别是在保险丝编程期间向钝化层的表面传输热波。

公开(公告)号：US5444287A

公开(公告)日：1995-08-22

申请号：US292901

申请日：1994-08-10

申请人： Raschid J. Bezama ,  Dominic J. Schepis ,  Krishna Seshan

发明人： Raschid J. Bezama ,  Dominic J. Schepis ,  Krishna Seshan

IPC分类号： H01H85/00 ,  H01H85/02 ,  H01H85/046 ,  H01H85/12 ,  H01L23/525 ,  H01L23/58 ,  H01L29/167 ,  H01L23/48 ,  H01L29/207

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  Y10S148/055

摘要： A noise immune fuse having sub-micron dimensions which can be programmed by an electrically and thermally synchronized event. The fuse includes a pair of fuse links in close proximity of each other, a layer of thermally conductive and electrically insulating material thermally coupling the two links forming the pair, and means for programming the first link by prompting the second link to gate the energy transfer between the links via the coupling layer. By combining thermal and electrical pulses to perform the programming function, the reliability of the fuse structure is greatly enhanced when compared to that of a single element fuse.

摘要翻译： 具有亚微米尺寸的噪声免疫保险丝，可通过电和热同步事件进行编程。 熔丝包括彼此紧密相邻的一对熔丝链，热耦合形成该对的两个连接的导热和电绝缘材料层，以及用于通过提示第二连接件对能量传递进行栅极编程的装置 通过耦合层在链路之间。 通过组合热和电脉冲来执行编程功能，与单个元件熔断器相比，熔丝结构的可靠性大大提高。

公开(公告)号：US5298784A

公开(公告)日：1994-03-29

申请号：US858835

申请日：1992-03-27

申请人： Jeffrey P. Gambino ,  Dominic J. Schepis ,  Krishna Seshan

发明人： Jeffrey P. Gambino ,  Dominic J. Schepis ,  Krishna Seshan

IPC分类号： H01L21/82 ,  H01L23/525 ,  H01L23/48

CPC分类号： H01L23/5256 ,  H01L23/5252 ,  H01L2924/0002

摘要： An improved antifuse uses metal penetration of either a P-N diode junction or a Schottky diode. The P-N junction, or Schottky diode, is contacted by a diffusion barrier such as TiN, W, Ti-W alloy, or layers of Ti and Cr, with a metal such as Al. Al-CU alloy, Cu, Au, or Ag on top of the diffusion barrier. When this junction is stressed with voltage pulse producing a high current density, severe joule heating occurs resulting in metal penetration of the diffusion barrier and the junction. The voltage drop across the junction decreases by about a factor of ten after the current stress and is stable thereafter. Alternatively, a shallow P-N junction in a silicon substrate is contacted by a layer of metal that forms a silicide, such as Ti, Cr, W, Mo, or Ta. Stressing the junction with a voltage pulse to produce a high current density results in the metal penetrating the junction and reacting with the substrate to form a silicide.

摘要翻译： 改进的反熔丝使用P-N二极管结或肖特基二极管的金属穿透。 P-N结或肖特基二极管通过诸如TiN，W，Ti-W合金或Ti和Cr的层的扩散阻挡层与诸如Al的金属接触。 Al-Cu合金，Cu，Au或Ag在扩散阻挡层的顶部。 当该结被电压脉冲施加而产生高电流密度时，发生严重的焦耳加热，导致扩散阻挡层和结的金属穿透。 跨接点的电压降在电流应力之后减少约十倍，此后稳定。 或者，硅衬底中的浅P-N结与由Ti，Cr，W，Mo或Ta形成硅化物的金属层接触。 用电压脉冲强加结以产生高电流密度导致金属穿透接合部并与衬底反应形成硅化物。

公开(公告)号：US5213249A

公开(公告)日：1993-05-25

申请号：US890988

申请日：1992-05-29

申请人： David C. Long ,  Krishna Seshan

发明人： David C. Long ,  Krishna Seshan

IPC分类号： B23K20/10 ,  H01L21/00

CPC分类号： H01L21/67253 ,  B23K20/10 ,  H01L24/75 ,  H01L24/78 ,  H01L24/81 ,  H01L24/85 ,  H01L2224/78 ,  H01L2224/85205 ,  H01L2224/859 ,  H01L2924/00014 ,  H01L2924/15787

摘要： An ultrasonic adhesion/dehesion monitoring apparatus for monitoring the adhesion/dehesion between first and second substrates comprising: a. an ultrasonic source for transmitting ultrasonic energy to at least first and second substrates; b. means for measuring the instantaneous AC current and instantaneous AC supplied to said ultrasonic source; c. means for multiplying the instantaneous AC voltage and the instantaneous AC current to determine the instantaneous power supplied to said ultrasonic source; and d. monitor means coupled to said ultrasonic source and said power determining means for monitoring the instantaneous power supplied to said ultrasonic source. Also disclosed is a method for monitoring the quality and/or adhesion/dehesion between first and second substrates in the ultrasonic adhesion/dehesion monitoring apparatus.

摘要翻译： 一种用于监测第一和第二基底之间的粘合/粘合的超声粘附/粘合监测装置，包括：a。 用于将超声波能量传输到至少第一和第二基底的超声波源; b。 用于测量提供给所述超声波源的瞬时AC电流和瞬时AC的装置; C。 用于将瞬时AC电压和瞬时AC电流相乘以确定提供给所述超声波源的瞬时功率的装置; 和d。 监视器装置，耦合到所述超声波源和所述功率确定装置，用于监视提供给所述超声波源的瞬时功率。 还公开了一种用于在超声波粘合/粘合监测装置中监测第一和第二基板之间的质量和/或粘附/粘合的方法。