公开(公告)号：US11908876B2

公开(公告)日：2024-02-20

申请号：US17517705

申请日：2021-11-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuki Okamoto ,  Yoshiyuki Kurokawa ,  Hiroki Inoue ,  Takuro Ohmaru

IPC: H01L27/146 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/12 ,  H04N23/54 ,  H01L29/786 ,  H01L31/075 ,  H01L23/528

CPC classification number: H01L27/14603 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/146 ,  H01L27/1461 ,  H01L27/1463 ,  H01L27/14609 ,  H01L27/14612 ,  H01L27/14616 ,  H01L27/14643 ,  H01L27/14692 ,  H01L29/7869 ,  H01L31/075 ,  H04N23/54 ,  H01L23/5286

Abstract: A solid-state imaging device with high productivity and improved dynamic range is provided. In the imaging device including a photoelectric conversion element having an i-type semiconductor layer, functional elements, and a wiring, an area where the functional elements and the wiring overlap with the i-type semiconductor in a plane view is preferably less than or equal to 35%, further preferably less than or equal to 15%, and still further preferably less than or equal to 10% of the area of the i-type semiconductor in a plane view. Plural photoelectric conversion elements are provided in the same semiconductor layer, whereby a process for separating the respective photoelectric conversion elements can be reduced. The respective i-type semiconductor layers in the plural photoelectric conversion elements are separated by a p-type semiconductor layer or an n-type semiconductor layer.

公开(公告)号：US11777502B2

公开(公告)日：2023-10-03

申请号：US17441804

申请日：2020-03-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroki Inoue ,  Munehiro Kozuma ,  Takeshi Aoki ,  Shuji Fukai ,  Fumika Akasawa ,  Sho Nagao

IPC: H03K19/08 ,  H03K17/56 ,  H01L27/12 ,  H01L27/13

CPC classification number: H03K19/08 ,  H03K17/56 ,  H01L27/1207 ,  H01L27/13

Abstract: A semiconductor device is provided; the semiconductor device includes unipolar transistors. A steady-state current does not flow in the semiconductor device. The semiconductor device uses a high-level potential and a low-level potential to express a high level and a low level, respectively. The semiconductor device includes unipolar transistors, a capacitor, first and second input terminals, and an output terminal. To the second input terminal, a signal is input whose logic is inverted from the logic of a signal input to the first input terminal. The semiconductor device has a circuit structure called bootstrap in which two unipolar transistors are connected in series between the high-level potential and the low-level potential and a capacitor is provided between an output terminal and a gate of one of the two transistors. A delay is caused between the gate of the transistor and the signal output from the output terminal, whereby the bootstrap can be certainly performed.

公开(公告)号：US11556771B2

公开(公告)日：2023-01-17

申请号：US16603710

申请日：2018-04-02

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shintaro Harada ,  Hiroki Inoue ,  Takeshi Aoki

IPC: G11C11/40 ,  G11C11/54 ,  G11C7/10 ,  G06N3/063

Abstract: Novel connection between neurons of a neural network is provided.
A perceptron included in the neural network includes a plurality of neurons; the neuron includes a synapse circuit and an activation function circuit; and the synapse circuit includes a plurality of memory cells. A bit line selected by address information for selecting a memory cell is shared by a plurality of perceptrons. The memory cell is supplied with a weight coefficient of an analog signal, and the synapse circuit is supplied with an input signal. The memory cell multiplies the input signal by the weight coefficient and converts the multiplied result into a first current. The synapse circuit generates a second current by adding a plurality of first currents and converts the second current into a first potential. The activation function circuit is a semiconductor device that converts the first potential into a second potential by a ramp function and supplies the second potential as an input signal of the synapse circuit included in the perceptron in a next stage.

公开(公告)号：US11205669B2

公开(公告)日：2021-12-21

申请号：US15311261

申请日：2015-05-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuki Okamoto ,  Yoshiyuki Kurokawa ,  Hiroki Inoue ,  Takuro Ohmaru

IPC: H01L27/146 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/12 ,  H01L29/786 ,  H01L31/075 ,  H04N5/225

Abstract: A solid-state imaging device with high productivity and improved dynamic range is provided. In the imaging device including a photoelectric conversion element having an i-type semiconductor layer, functional elements, and a wiring, an area where the functional elements and the wiring overlap with the i-type semiconductor in a plane view is preferably less than or equal to 35%, further preferably less than or equal to 15%, and still further preferably less than or equal to 10% of the area of the i-type semiconductor in a plane view. Plural photoelectric conversion elements are provided in the same semiconductor layer, whereby a process for separating the respective photoelectric conversion elements can be reduced. The respective i-type semiconductor layers in the plural photoelectric conversion elements are separated by a p-type semiconductor layer or an n-type semiconductor layer.

公开(公告)号：US10128249B2

公开(公告)日：2018-11-13

申请号：US15390957

申请日：2016-12-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Fumika Akasawa ,  Hiroki Inoue ,  Takashi Nakagawa ,  Yoshiyuki Kurokawa

IPC: H01L27/108 ,  H01L21/8242 ,  G11C8/08 ,  G11C11/405 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/403

Abstract: To provide a semiconductor device that can reduce power consumption and retain data for a long time and a memory device including the semiconductor device. The semiconductor device includes a word line divider, a memory cell, a first wiring, and a second wiring. The word line divider is electrically connected to the first wiring and the second wiring. The memory cell includes a first transistor with a dual-gate structure. A first gate of the first transistor is electrically connected to the first wiring, and a second gate of the first transistor is electrically connected to the second wiring. The word line divider supplies a high-level potential or a low-level potential to the first wiring and supplies a predetermined potential to the second wiring, whereby a threshold voltage of the first transistor is changed. With such a configuration, a semiconductor device that can reduce power consumption and retain data for a long time is driven.

公开(公告)号：US09870827B2

公开(公告)日：2018-01-16

申请号：US15359017

申请日：2016-11-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takashi Nakagawa ,  Hiroki Inoue ,  Fumika Akasawa ,  Yoshiyuki Kurokawa

IPC: G11C16/04 ,  G11C11/34 ,  G11C16/10 ,  H01L27/12 ,  H01L27/146

CPC classification number: G11C16/10 ,  G11C7/1006 ,  G11C7/16 ,  G11C8/12 ,  G11C11/405 ,  G11C11/4087 ,  G11C16/0466 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/14616 ,  H01L27/14636 ,  H01L27/14643

Abstract: A semiconductor device with an arithmetic processing function is provided. The semiconductor device includes a first circuit and a second circuit each having a function of performing one-dimensional discrete cosine transform. By directly inputting output data of the first circuit to the second circuit, two-dimensional discrete cosine transform can be performed immediately. A memory cell array included in the first circuit is divided into a plurality of memory blocks. In the case where a selection transistor is provided in the memory block, data processing can be performed in each memory block.

公开(公告)号：US09601429B2

公开(公告)日：2017-03-21

申请号：US15090733

申请日：2016-04-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takanori Matsuzaki ,  Hiroki Inoue

IPC: G11C11/24 ,  H01L23/528 ,  H01L29/24 ,  H01L29/16 ,  H01L27/12 ,  H01L29/786 ,  G11C7/10 ,  G11C11/56 ,  G11C11/40 ,  G11C15/04 ,  G11C15/00 ,  G11C11/404

CPC classification number: H01L23/528 ,  G11C7/1048 ,  G11C7/1051 ,  G11C11/24 ,  G11C11/40 ,  G11C11/404 ,  G11C11/56 ,  G11C11/5621 ,  G11C11/5642 ,  G11C15/00 ,  G11C15/04 ,  G11C15/046 ,  H01L27/1207 ,  H01L29/16 ,  H01L29/24 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A highly reliable semiconductor device. In a configuration where a precharged source line is discharged to a bit line by establishing electrical continuity between the source line and the bit line through a transistor to read a potential retained at a gate of the transistor, the potential of the bit line is switched in accordance with a change in potential of the source line due to the discharge. With this configuration, the voltage between the source and drain of the transistor can be kept lower than a predetermined voltage by discharge. Accordingly, the source-drain voltage of the transistor can be kept lower than its breakdown voltage, so that the semiconductor device can have high reliability.

公开(公告)号：US09391598B2

公开(公告)日：2016-07-12

申请号：US15001338

申请日：2016-01-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroki Inoue ,  Kei Takahashi ,  Tatsuya Onuki

IPC: H03L5/00 ,  H03K5/24

CPC classification number: H03K5/2481 ,  G11C27/024 ,  G11C27/026 ,  H03K5/249

Abstract: A sample-and-hold circuit including a transistor and a capacitor is connected to the differential circuit. The sample-and-hold circuit acquires voltage for correcting the offset voltage of the differential circuit by charging or discharging the capacitor through sampling operation. Then, it holds the potential of the capacitor through holding operation. In normal operation of the differential circuit, the output potential of the differential circuit is corrected by the potential held by the capacitor. The transistor in the sample-and-hold circuit is preferably a transistor whose channel is formed using an oxide semiconductor. An oxide semiconductor transistor has extremely low leakage current; thus, a change in the potential held in the capacitor of the sample-and-hold circuit can be minimized.

Abstract translation: 包括晶体管和电容器的采样保持电路连接到差分电路。 采样保持电路通过采样操作对电容器进行充电或放电来获取用于校正差分电路的偏移电压的电压。 然后，它通过保持操作保持电容器的电位。 在差分电路的正常工作中，差分电路的输出电位由电容器保持的电位进行校正。 采样保持电路中的晶体管优选地是使用氧化物半导体形成沟道的晶体管。 氧化物半导体晶体管具有极低的漏电流; 因此，可以使采样保持电路的电容器中保持的电位变化最小化。

公开(公告)号：US09196345B2

公开(公告)日：2015-11-24

申请号：US14288894

申请日：2014-05-28

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hiroki Inoue ,  Takanori Matsuzaki ,  Tomoaki Atsumi

IPC: G11C7/12 ,  G11C7/06 ,  G11C11/403 ,  G11C11/4076 ,  G11C11/4094

CPC classification number: G11C11/403 ,  G11C11/4076 ,  G11C11/4094

Abstract: In a memory cell including first to third transistors, the potential of a bit line is set to VDD or GND when data is written through the first transistor. In a standby period, the potential of the bit line is set to GND. In reading operation, the bit line is brought into a floating state at GND, and a source line is set to a potential VDD−α, consequently, the third transistor is turned on. Then, the potential of the source line is output according to the potential of a gate of the second transistor. Note that α is set so that the second transistor is surely off even when the potential of the gate of the second transistor becomes lower from VDD by ΔV in the standby period. That is, Vth+ΔV

Abstract translation: 在包括第一至第三晶体管的存储单元中，当通过第一晶体管写入数据时，位线的电位被设置为VDD或GND。 在待机期间，位线的电位设置为GND。 在读取操作中，位线处于GND处的浮置状态，源极线被设置为电位VDD-α，因此第三晶体管导通。 然后，根据第二晶体管的栅极的电位输出源极线的电位。 注意，设置α，使得即使在待机期间第二晶体管的栅极的电位从VDD降低了＆Dgr; V，第二晶体管也可靠地关断。 也就是说，Vth +＆Dgr; V <α，其中Vth是第二晶体管的阈值。

公开(公告)号：US09153589B2

公开(公告)日：2015-10-06

申请号：US13900581

申请日：2013-05-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato ,  Shuhei Nagatsuka ,  Takanori Matsuzaki ,  Hiroki Inoue

IPC: H01L29/788 ,  H01L27/108 ,  H01L27/115 ,  G11C16/04 ,  H01L27/105 ,  H01L27/12 ,  H01L27/11 ,  H01L49/02

CPC classification number: H01L29/7869 ,  G11C16/0425 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10805 ,  H01L27/11 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/11563 ,  H01L27/11568 ,  H01L27/1225 ,  H01L28/40 ,  H01L29/78693 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792

Abstract: The semiconductor device includes a source line, a bit line, a signal line, a word line, memory cells connected in parallel between the source line and the bit line, a first driver circuit electrically connected to the source line and the bit line through switching elements, a second driver circuit electrically connected to the source line through a switching element, a third driver circuit electrically connected to the signal line, and a fourth driver circuit electrically connected to the word line. The memory cell includes a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, a second transistor including a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor. The second transistor includes an oxide semiconductor material.

Abstract translation: 半导体器件包括源极线，位线，信号线，字线，在源极线和位线之间并联连接的存储器单元，通过开关电连接到源极线和位线的第一驱动器电路 元件，通过开关元件电连接到源极线的第二驱动器电路，电连接到信号线的第三驱动电路，以及电连接到字线的第四驱动电路。 存储单元包括第一晶体管，包括第一栅电极，第一源电极和第一漏电极，第二晶体管包括第二栅电极，第二源电极和第二漏极，以及电容器。 第二晶体管包括氧化物半导体材料。