公开(公告)号：US20230260832A1

公开(公告)日：2023-08-17

申请号：US17831884

申请日：2022-06-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Kai Lin ,  Po-Cheng Shih ,  Jr-Hung Li ,  Tze-Liang Lee

IPC: H01L21/768 ,  H01L23/535 ,  H01L23/532 ,  H01L21/02

CPC classification number: H01L21/76829 ,  H01L21/0228 ,  H01L21/02178 ,  H01L21/02205 ,  H01L21/76843 ,  H01L21/76895 ,  H01L23/535 ,  H01L23/53266

Abstract: Semiconductor devices and methods of manufacture are presented herein in which a etch stop layer is selectively deposited over a conductive contact. A dielectric layer is formed over the etch stop layer and an opening is formed through the dielectric layer and the etch stop layer to expose the conductive contact. Conductive material is then deposited to fill the opening.

公开(公告)号：US11725278B2

公开(公告)日：2023-08-15

申请号：US16723643

申请日：2019-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kun-Mo Lin ,  Yi-Hung Lin ,  Jr-Hung Li ,  Tze-Liang Lee ,  Ting-Gang Chen ,  Chung-Ting Ko

IPC: C23C16/455 ,  H01J37/32 ,  C23C16/509 ,  H01L21/02 ,  H01L21/285

CPC classification number: C23C16/45536 ,  C23C16/45551 ,  C23C16/45565 ,  C23C16/509 ,  H01J37/3244 ,  H01J37/32091 ,  H01J37/32357 ,  H01J37/32366 ,  H01J37/32449 ,  H01J37/32522 ,  H01J37/32532 ,  H01J37/32541 ,  H01L21/0228 ,  H01L21/0262 ,  H01L21/02274 ,  H01L21/28556

Abstract: A system and method for plasma enhanced deposition processes. An exemplary semiconductor manufacturing system includes a susceptor configured to hold a semiconductor wafer and a sector disposed above the susceptor. The sector includes a first plate and an overlying second plate, operable to form a plasma there between. The first plate includes a plurality of holes extending through the first plate, which vary in at least one of diameter and density from a first region of the first plate to a second region of the first plate.

公开(公告)号：US11705332B2

公开(公告)日：2023-07-18

申请号：US17150403

申请日：2021-01-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen Kuo ,  Chih-Cheng Liu ,  Ming-Hui Weng ,  Jia-Lin Wei ,  Yen-Yu Chen ,  Jr-Hung Li ,  Yahru Cheng ,  Chi-Ming Yang ,  Tze-Liang Lee ,  Ching-Yu Chang

IPC: H01L21/00 ,  H01L21/027 ,  H01L21/02

CPC classification number: H01L21/0275 ,  H01L21/0228 ,  H01L21/02362

Abstract: A method of forming a pattern in a photoresist layer includes forming a photoresist layer over a substrate, and reducing moisture or oxygen absorption characteristics of the photoresist layer. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.

公开(公告)号：US20230197524A1

公开(公告)日：2023-06-22

申请号：US18168383

申请日：2023-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yi Lee ,  Hong-Hsien Ke ,  Chung-Ting Ko ,  Chia-Hui Lin ,  Jr-Hung Li

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/311 ,  C23C16/34 ,  C23C16/455

CPC classification number: H01L21/823468 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/02211 ,  H01L21/31116 ,  H01L21/823431 ,  C23C16/345 ,  C23C16/45542 ,  H01L21/0217 ,  H01L21/0228

Abstract: An etch stop layer is formed over a semiconductor fin and gate stack. The etch stop layer is formed utilizing a series of pulses of precursor materials. A first pulse introduces a first precursor material to the semiconductor fin and gate stack. A second pulse introduces a second precursor material, which is turned into a plasma and then directed towards the semiconductor fin and gate stack in an anisotropic deposition process. As such, a thickness of the etch stop layer along a bottom surface is larger than a thickness of the etch stop layer along sidewalls.

公开(公告)号：US11289417B2

公开(公告)日：2022-03-29

申请号：US16805834

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Chou ,  Jr-Hung Li ,  Liang-Yin Chen ,  Su-Hao Liu ,  Tze-Liang Lee ,  Meng-Han Chou ,  Kuo-Ju Chen ,  Huicheng Chang ,  Tsai-Jung Ho ,  Tzu-Yang Ho

IPC: H01L23/522 ,  H01L29/08 ,  H01L23/532 ,  H01L29/66 ,  H01L21/768 ,  H01L21/3105 ,  H01L29/78 ,  H01L21/02 ,  H01L23/528 ,  H01L29/06

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.

公开(公告)号：US11239309B2

公开(公告)日：2022-02-01

申请号：US16704138

申请日：2019-12-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Wen Wu ,  Fu-Kai Yang ,  Chen-Ming B. Lee ,  Mei-Yun Wang ,  Jr-Hung Li ,  Bo-Cyuan Lu

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/762 ,  H01L21/32

Abstract: Semiconductor devices and methods of fabricating semiconductor devices are provided. The present disclosure provides a semiconductor device that includes a first fin structure and a second fin structure each extending from a substrate; a first gate segment over the first fin structure and a second gate segment over the second fin structure; a first isolation feature separating the first and second gate segments; a first source/drain (S/D) feature over the first fin structure and adjacent to the first gate segment; a second S/D feature over the second fin structure and adjacent to the second gate segment; and a second isolation feature also disposed in the trench. The first and second S/D features are separated by the second isolation feature, and a composition of the second isolation feature is different from a composition of the first isolation feature.

公开(公告)号：US20220028684A1

公开(公告)日：2022-01-27

申请号：US17156365

申请日：2021-01-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yen-Yu CHEN ,  Chib-Cheng LIU ,  Yi-Ohen KUO ,  Jr-Hung Li ,  Tze-Liang LEE ,  Ming-Hui WENG ,  Yahru CHENG

IPC: H01L21/027 ,  H01L21/311 ,  H01L21/308

Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate and forming a dehydrated film over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation to form an exposed portion and an unexposed portion of the photoresist layer. The photoresist layer is developed to remove the unexposed portion of the photoresist layer and a first portion of the dehydrated film over the unexposed portion of the photoresist layer. In an embodiment, the method includes etching the substrate by using the exposed portion of the photoresist layer as a mask.

公开(公告)号：US20210098584A1

公开(公告)日：2021-04-01

申请号：US16805862

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hsien Cheng ,  Jr-Hung Li ,  Tai-Chun Huang ,  Tze-Liang Lee ,  Chung-Ting Ko ,  Jr-Yu Chen ,  Wan-Chen Hsieh

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, a source/drain (S/D) region and a contact. The S/D region is located in the substrate and on a side of the gate structure. The contact lands on and connected to the S/D region. The contact wraps around the S/D region.

公开(公告)号：US20200075419A1

公开(公告)日：2020-03-05

申请号：US16674443

申请日：2019-11-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Cyuan Lu ,  Chunyao Wang ,  Jr-Hung Li ,  Chung-Ting Ko ,  Chi On Chui

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/423 ,  H01L29/417 ,  H01L29/78

Abstract: Gate structures and gate spacers, along with methods of forming such, are described. In an embodiment, a structure includes an active area on a substrate, a gate structure on the active area and over the substrate, and a low-k gate spacer on the active area and along a sidewall of the gate structure. The gate structure includes a conformal gate dielectric on the active area and includes a gate electrode over the conformal gate dielectric. The conformal gate dielectric extends vertically along a first sidewall of the low-k gate spacer. In some embodiments, the low-k gate spacer can be formed using a selective deposition process after a dummy gate structure has been removed in a replacement gate process.