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66 条记录 (耗时 0.026 秒)

    Constant current source circuit
    41.
    发明申请
    Constant current source circuit 有权
    恒流源电路

    公开(公告)号：US20090085550A1

    公开(公告)日：2009-04-02

    申请号：US12285089

    申请日：2008-09-29

    申请人： Akira Ide

    发明人： Akira Ide

    IPC分类号： G05F3/16

    CPC分类号： G05F3/16 ,  G05F3/262

    摘要： A constant current source circuit is constituted of a control voltage generation section which detects the output voltage at the output terminal so as to generate a control voltage, a reference current adjustment section which adjust a reference current based on the control voltage, and a current mirror section which outputs the output current responsive to the adjusted reference current at the output terminal. This reduces variations of the output current due to variations of the output voltage; hence, the constant current source circuit can precisely operate in a low-voltage region.

    摘要翻译： 恒流源电路由检测输出端子的输出电压以产生控制电压的控制电压产生部分，基于控制电压调整参考电流的参考电流调节部分和电流镜 该部分响应于在输出端子处调整的参考电流而输出输出电流。 这可以减少由于输出电压的变化引起的输出电流的变化; 因此，恒流源电路可以在低电压区域中精确地工作。

    Semiconductor device
    42.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US06717833B2

    公开(公告)日：2004-04-06

    申请号：US09750625

    申请日：2000-12-12

    申请人： Goro Kitsukawa ,  Yoji Idei ,  Kanji Oishi ,  Akira Ide

    发明人： Goro Kitsukawa ,  Yoji Idei ,  Kanji Oishi ,  Akira Ide

    IPC分类号： G11C506

    CPC分类号： G11C7/10

    摘要： A 64Mb DRAM includes memory cell array areas 15, sense amplifier areas 16, subword driver areas 17, and cross areas 18. For each horizontal input/output line IOH paraleel to the word line W, throuh holes on the sense amplifiers provide connections between the second metal line hierarchy M2 and the third metal line hierarchy M3. The vertical input/output line IOV parallel to the bit line BL runs through a plurality of memory cell array areas 15 in a direction parallel to the column selection signal line YS and connects to the main amplifier MA outside the memory cell array areas 15. In this input/output line configuration, the greater the number of word lines W that are selected, the greater the number of bits that can be output.

    摘要翻译： 64Mb DRAM包括存储单元阵列区域15，读出放大器区域16，子字驱动器区域17和交叉区域18.对于到字线W的每个水平输入/输出线路IOH路由器，传感放大器上的孔洞提供 第二金属线层级M2和第三金属线层级M3。 与位线BL并联的垂直输入/输出线IOV沿与列选择信号线YS平行的方向延伸穿过多个存储单元阵列区域15，并连接到存储单元阵列区域15外的主放大器MA。 该输入/输出线配置，所选择的字线W的数量越大，可以输出的位数越大。

    Semiconductor integrated circuit having logic gates
    43.
    发明授权
    Semiconductor integrated circuit having logic gates 失效
    具有逻辑门的半导体集成电路

    公开(公告)号：US5544125A

    公开(公告)日：1996-08-06

    申请号：US383866

    申请日：1995-02-06

    申请人： Yuji Yokoyama ,  Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Nobuyuki Gotou ,  Akira Ide

    发明人： Yuji Yokoyama ,  Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Nobuyuki Gotou ,  Akira Ide

    IPC分类号： G11C7/10 ,  G11C8/10 ,  H03K19/0948 ,  G11C8/00

    CPC分类号： H03K19/0948 ,  G11C7/1051 ,  G11C7/1078 ,  G11C8/10

    摘要： An arrangement which is particularly effective for decoders in semiconductor memory circuits which use, for example, common NMOS to receive one input for a plurality of logic decoder gates is provided includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals, and each being coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. An improved read/write arrangement is also provided for such semiconductor memory circuits which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.

    摘要翻译： 提供了对于使用例如公共NMOS来接收多个逻辑解码器门的一个输入的半导体存储器电路中的解码器特别有效的装置，其包括多个逻辑门，每个逻辑门具有用于分别接收第一输入的第一输入端 信号，并且每个都耦合到公共节点。 在一个实施例中，第一和第二开关元件也耦合到公共节点。 第一和第二开关元件都耦合到第二输入端子，用于接收多个逻辑门公共的第二输入信号，并且它们都响应于第二输入信号互相互补。 还提供了一种改进的读/写布置，用于这样的半导体存储器电路，其包括在写入操作期间防止公共读取线与数据线连接的电路。 这通过在写入期间去除公共读取线的负载来增强写入速度。

    Bipolar MOS logic circuit and semiconductor integrated circuit
    45.
    发明授权
    Bipolar MOS logic circuit and semiconductor integrated circuit 失效
    双极MOS逻辑电路和半导体集成电路

    公开(公告)号：US5057713A

    公开(公告)日：1991-10-15

    申请号：US486419

    申请日：1990-02-28

    申请人： Masahiro Iwamura ,  Akira Ide

    发明人： Masahiro Iwamura ,  Akira Ide

    IPC分类号： H03K17/04 ,  H03K17/567 ,  H03K19/00 ,  H03K19/013 ,  H03K19/08 ,  H03K19/0944

    CPC分类号： H03K19/09448 ,  H03K19/001 ,  H03K19/0136

    摘要： An invention is disclosed, which is suitable for operating a bipolar-MOS logic circuit, and in particular Bi-CMOS logic circuit with a low power supply voltage below 5V, e.g. around 3V. According to the present logic circuit, since the base current of a second NPN transistor is supplied from a power supply through a PMOS transistor (first current switching means), the impedance of which is lowered previously by a logic inverting means and an NMOS logic circuit (second current switching means), which is on/off controlled by an input signal, in a transient logic level transition period where the output is switched from the level "1" to "0" (i.e. it falls), it is possible to supply a sufficient base current to the second NPN. In this way, it is possible to turn-on the second NPN with a high speed and to pull down to the level "0" with high speed. Further, since the PMOS is switched off owing to the action of the logic inverting means just after having allowed a sufficient base current flow therethrough, the current path, through which the base current of the second NPN is supplied, is stopped and thus DC power consumption is elimated.

    摘要翻译： 公开了一种适用于操作双极MOS逻辑电路的发明，特别是具有低于5V的低电源电压的Bi-CMOS逻辑电路，例如， 3V左右 根据本逻辑电路，由于第二NPN晶体管的基极电流通过PMOS晶体管（第一电流开关装置）从电源提供，其阻抗先前由逻辑反相装置和NMOS逻辑电路 （第二电流切换装置），其在输出从电平“1”切换到“0”的瞬态逻辑电平转换周期（即，其下降）中，其由输入信号控制的开/关控制， 向第二NPN提供足够的基极电流。 以这种方式，可以高速打开第二个NPN并以高速下拉到“0”电平。 此外，由于刚刚在允许足够的基极电流流动之后由于逻辑反相装置的作用使PMOS截止，所以提供第二NPN的基极电流的电流通路被停止，因此直流电力 消费被淘汰。

    Process for cleaning mercury-containing gaseous emissions
    46.
    发明授权
    Process for cleaning mercury-containing gaseous emissions 失效
    清洁含汞气体排放的方法

    公开(公告)号：US4729882A

    公开(公告)日：1988-03-08

    申请号：US772236

    申请日：1985-09-03

    申请人： Akira Ide ,  Tsutomu Shigenaka ,  Masayuki Kokado ,  Shigeru Kondo

    发明人： Akira Ide ,  Tsutomu Shigenaka ,  Masayuki Kokado ,  Shigeru Kondo

    IPC分类号： B01D53/64 ,  B01D53/34

    CPC分类号： B01D53/64

    摘要： A process for cleaning gaseous emissions containing mercury (Hg) comprises the steps of adding a chlorine-containing material to the mercury-containing gaseous emissions and heating the mixture to convert the mercury into water-soluble mercuric chloride (HgCl.sub.2); scrubbing the water-soluble mercuric chloride with wash water and fixing the same as chlorocomplex ion (HgCl.sub.4.sup.-2) stable in liquid; and thereafter subjecting the washings from the scrubbing step to coagulating sedimentation and thereby fixing and insolubilizing the mercury in the resulting sludge.

    摘要翻译： 用于清洁含有汞（Hg）的气体排放物的方法包括以下步骤：向含汞气体排放物中加入含氯物质并加热混合物以将汞转化成水溶性氯化汞（HgCl 2）; 用洗涤水洗涤水溶性氯化汞，并将其固定在液体中稳定的氯仿复合离子（HgCl4-2）; 然后对来自洗涤步骤的洗涤液进行凝结沉淀，从而固定和不溶解所得污泥中的汞。

    Semiconductor device
    47.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08981558B2

    公开(公告)日：2015-03-17

    申请号：US13440583

    申请日：2012-04-05

    申请人： Akira Ide

    发明人： Akira Ide

    IPC分类号： H01L23/48 ,  H01L23/498 ,  H01L23/544 ,  H01L25/065 ,  H01L21/768 ,  H01L23/522 ,  H01L25/00

    CPC分类号： H01L23/498 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/522 ,  H01L23/544 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2924/15311

    摘要： A semiconductor device includes a multi-level wiring structure that includes a first wring layer, a plurality of first patterns, and a first mark. The first wring layer is disposed at a first wiring level of the multi-level wiring structure. The plurality of first patterns is disposed over the first wring layer. The plurality of first patterns is disposed at a second wiring level of the multi-level wiring structure. The second wiring level is above the first wiring level. The plurality of first patterns is disposed over the first wring layer. The plurality of first patterns is disposed at a second wiring level of the multi-level wiring structure. The second wiring level is above the first wiring level. The first mark is disposed over the first wring layer. The first mark is disposed at a third wiring level. The third wiring level is above the second wiring level.

    摘要翻译： 半导体器件包括多级布线结构，其包括第一绞合层，多个第一图案和第一标记。 第一绞合层设置在多层布线结构的第一布线层。 多个第一图案设置在第一拧紧层上。 多个第一图案设置在多层布线结构的第二布线层。 第二个接线电平高于第一个接线电平。 多个第一图案设置在第一拧紧层上。 多个第一图案设置在多层布线结构的第二布线层。 第二个接线电平高于第一个接线电平。 第一标记设置在第一绞合层上。 第一标记设置在第三布线层。 第三个接线电平高于第二个接线电平。

    Semiconductor device having plural memory chip
    49.
    发明授权
    Semiconductor device having plural memory chip 有权
    具有多个存储芯片的半导体器件

    公开(公告)号：US08924903B2

    公开(公告)日：2014-12-30

    申请号：US13288631

    申请日：2011-11-03

    申请人： Akira Ide

    发明人： Akira Ide

    IPC分类号： G06F17/50 ,  G11C5/04 ,  H01L25/065 ,  H01L23/48

    CPC分类号： H01L25/0657 ,  G11C5/04 ,  G11C11/408 ,  H01L23/481 ,  H01L23/50 ,  H01L2224/16145 ,  H01L2225/06544

    摘要： A semiconductor device includes a stacked plurality of memory chips. The memory chips each include a plurality of memory banks, a plurality of read/write buses that are assigned to the respective memory banks, and a plurality of penetration electrodes that are assigned to the respective read/write buses and arranged through the memory chip. Penetration electrodes arranged in the same positions as seen in a stacking direction are connected in common between the chips. In response to an access request, the memory chips activate the memory banks that are arranged in respective different positions as seen in the stacking direction, whereby data is simultaneously input/output via the penetration electrodes that lie in different planar positions.

    摘要翻译： 半导体器件包括堆叠的多个存储器芯片。 存储器芯片各自包括多个存储体，分配给各个存储体的多个读/写总线和分配给各个读/写总线并经由存储芯片布置的多个贯穿电极。 布置在层叠方向上看到的相同位置的穿透电极在芯片之间共同连接。 响应于访问请求，存储器芯片激活被布置在层叠方向上的各个不同位置的存储体，由此通过位于不同平面位置的穿透电极同时输入/输出数据。

    SEMICONDUCTOR DEVICE HAVING OPTICAL FUSE AND ELECTRICAL FUSE
    50.
    发明申请
    SEMICONDUCTOR DEVICE HAVING OPTICAL FUSE AND ELECTRICAL FUSE 有权
    具有光电保险丝和电保险丝的半导体器件

    公开(公告)号：US20140141543A1

    公开(公告)日：2014-05-22

    申请号：US14162671

    申请日：2014-01-23

    申请人： Akira Ide ,  MANABU ISHIMATSU ,  KENTARO HARA

    发明人： Akira Ide ,  MANABU ISHIMATSU ,  KENTARO HARA

    IPC分类号： H01L21/66

    CPC分类号： H01L22/14 ,  G11C7/24 ,  G11C29/787 ,  G11C29/789 ,  G11C29/802 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for manufacturing a stacked semiconductor memory device includes testing a plurality of memory chips to detect first defective addresses, programming optical fuses with first defective address information on each of the plurality of memory chips that have the first defective addresses, stacking the plurality of memory chips, testing the stacked memory chips to detect second defective addresses, and programming electrical fuses with second defective address information.

    摘要翻译： 一种用于制造叠层半导体存储器件的方法包括测试多个存储器芯片以检测第一缺陷地址，对具有第一缺陷地址的多个存储器芯片中的每一个上的第一缺陷地址信息编程光学熔丝，堆叠多个存储器 芯片，测试堆叠的存储器芯片以检测第二个缺陷地址，以及编程具有第二缺陷地址信息的电熔丝。