公开(公告)号：US06998307B2

公开(公告)日：2006-02-14

申请号：US10650055

申请日：2003-08-26

申请人： Bernhard Sell ,  Annette Sänger ,  Dirk Schumann

发明人： Bernhard Sell ,  Annette Sänger ,  Dirk Schumann

IPC分类号： H01L21/8242

CPC分类号： H01L27/10861 ,  H01L21/28518 ,  H01L21/31604 ,  H01L27/10814 ,  H01L28/60

摘要： The present invention relates to a novel method for fabricating a storage capacitor designed as a trench or a stacked capacitor and is used in particular in a DRAM memory cell. The method includes steps of forming a lower, metallic capacitor electrode, a storage dielectric and an upper capacitor electrode. The lower, metallic capacitor electrode is formed in a self-aligned manner on a silicon base material in such a way that uncovered silicon regions are first produced at locations at which the lower capacitor electrode will be formed, and then metal silicide is selectively formed on the uncovered silicon regions.

公开(公告)号：US20050099879A1

公开(公告)日：2005-05-12

申请号：US10944536

申请日：2004-09-17

申请人： Matthias Goldbach ,  Bernhard Sell

发明人： Matthias Goldbach ,  Bernhard Sell

IPC分类号： G11C7/06 ,  G11C11/4091 ,  G11C29/12 ,  G11C29/38 ,  G11C29/50 ,  G11C8/02

CPC分类号： G11C7/062 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/41 ,  G11C29/12 ,  G11C29/38 ,  G11C29/50

摘要： A circuit arrangement includes a bit line (10), a reference bit line (12), a sense amplifier with two cross-coupled CMOS inverters, which in each case comprise an n-channel transistor (20, 22) and a p-channel field-effect transistor (30, 32), and also, at the respective source terminals, two voltage sources (40, 42), of which the voltage source (40) linked to the n-channel field-effect transistors can be driven from a lower through to an upper potential and the voltage source (42) linked to the p-channel field-effect transistors (30, 32) can be driven from the upper through to the lower potential. With this circuit arrangement, it is possible to store three different charge states in the memory cell (4) on the bit line (10) if the threshold voltages (UTH1, UTH2) at the transistors are chosen to be greater than half the voltage difference between the lower and upper voltage potentials. This can be achieved by production engineering or, for example, by changing the substrate bias voltage. The third charge state can be utilized for binary logic or for detecting a defect in the memory cell (4).

摘要翻译： 电路装置包括位线（10），参考位线（12），具有两个交叉耦合CMOS反相器的读出放大器，其在每种情况下都包括n沟道晶体管（20,22）和p沟道 场效应晶体管（30,32），并且在相应的源极端处，两个电压源（40,42），其中连接到n沟道场效应晶体管的电压源（40）可以从 连接到p沟道场效应晶体管（30,32）的电压源（42）可以从上到下的电位驱动。 利用这种电路装置，如果阈值电压（U TH1，U2，...，TH2），则可以在位线（10）上的存储单元（4）中存储三种不同的电荷状态， SUB>）被选择为大于电压下限和下限之间的电压差的一半。 这可以通过生产工程来实现，或者例如通过改变衬底偏置电压来实现。 第三充电状态可用于二进制逻辑或用于检测存储器单元（4）中的缺陷。

公开(公告)号：US06797613B2

公开(公告)日：2004-09-28

申请号：US10196698

申请日：2002-07-16

申请人： Bernhard Sell ,  Annette Sänger ,  Georg Schulze-Icking

发明人： Bernhard Sell ,  Annette Sänger ,  Georg Schulze-Icking

IPC分类号： H01L21443

CPC分类号： H01L21/28556 ,  H01L21/28518

摘要： Tungsten silicide layers are formed on a substrate and a semiconductor component has deep trench capacitors with a filling of tungsten silicide. The tungsten silicide layers are deposited on the substrate at a temperature of less than 400° C. and at a pressure of less than 10 torr from the vapor phase. The vapor phase hs a tungsten-containing precursor substance and a silicon-containing precursor substance. The molar ratio of the silicon-containing precursor compound to the tungsten-containing precursor compound in the vapor phase is selected to be greater than 500.

摘要翻译： 在衬底上形成硅化钨层，并且半导体部件具有填充硅化钨的深沟槽电容器。 硅化钨层在低于400℃的温度和低于10托的压力下沉积在基底上。 气相hs是含钨前体物质和含硅前体物质。 气相中含硅前体化合物与含钨前体化合物的摩尔比选择为大于500。

公开(公告)号：US06620724B1

公开(公告)日：2003-09-16

申请号：US10142518

申请日：2002-05-09

申请人： Uwe Schroeder ,  Helmut Horst Tews ,  Irene McStay ,  Manfred Hauf ,  Matthias Goldbach ,  Bernhard Sell ,  Harald Seidl ,  Dirk Schumann ,  Rajarao Jammy ,  Joseph F. Shepard, Jr. ,  Jean-Marc Rousseau

发明人： Uwe Schroeder ,  Helmut Horst Tews ,  Irene McStay ,  Manfred Hauf ,  Matthias Goldbach ,  Bernhard Sell ,  Harald Seidl ,  Dirk Schumann ,  Rajarao Jammy ,  Joseph F. Shepard, Jr. ,  Jean-Marc Rousseau

IPC分类号： H01L214763

CPC分类号： H01L28/60 ,  H01L27/10861

摘要： Semiconductor devices having deep trenches with fill material therein having low resistivity are provided along with methods of fabricating such semiconductor devices.

摘要翻译： 提供其具有低电阻率的具有低填充材料的深沟槽的半导体器件以及制造这种半导体器件的方法。

公开(公告)号：US06541334B2

公开(公告)日：2003-04-01

申请号：US09891188

申请日：2001-06-25

申请人： Jörn Luetzen ,  Bernhard Sell

发明人： Jörn Luetzen ,  Bernhard Sell

IPC分类号： H01L218242

CPC分类号： H01L27/10861 ,  H01L27/1087

摘要： The integrated circuit configuration has at least one buried circuit element and an insulating layer. A multiplicity of insulating regions are in contact with one another to forming a locally delimited insulating layer in the substrate. In this way, trench capacitors implemented as buried circuit elements can be manufactured with a structure size of less than 100 nm in a simple and cost-effective manner.

公开(公告)号：US20170012132A1

公开(公告)日：2017-01-12

申请号：US15275072

申请日：2016-09-23

申请人： Bernhard Sell

发明人： Bernhard Sell

IPC分类号： H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L29/08 ,  H01L29/10

CPC分类号： H01L21/823431 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/823412 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7853

摘要： Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.

摘要翻译： 描述了半导体器件的半导体器件和形成具有不同宽度的半导体器件的方法。 例如，半导体器件包括设置在衬底上方的半导体本体。 栅电极堆叠设置在半导体本体的一部分上，以在栅电极堆叠下方限定半导体本体中的沟道区。 源极和漏极区域限定在栅电极堆叠的任一侧上的半导体本体中。 侧壁间隔件邻近栅极电极堆叠并且仅在源极和漏极区域的一部分上设置。 侧壁间隔物下方的源区和漏区的部分具有高于半导体本体的沟道区的高度和宽度的高度和宽度。

公开(公告)号：US20150147863A1

公开(公告)日：2015-05-28

申请号：US14569166

申请日：2014-12-12

申请人： Bernhard Sell

发明人： Bernhard Sell

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L21/308 ,  H01L29/16 ,  H01L21/306

CPC分类号： H01L21/823431 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/823412 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7853

摘要： Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.

摘要翻译： 描述了半导体器件的半导体器件和形成具有不同宽度的半导体器件的方法。 例如，半导体器件包括设置在衬底上方的半导体本体。 栅电极堆叠设置在半导体本体的一部分上，以在栅电极堆叠下方限定半导体本体中的沟道区。 源极和漏极区域限定在栅电极堆叠的任一侧上的半导体本体中。 侧壁间隔件邻近栅极电极堆叠并且仅在源极和漏极区域的一部分上设置。 侧壁间隔物下方的源区和漏区的部分具有高于半导体本体的沟道区的高度和宽度的高度和宽度。

公开(公告)号：US08803245B2

公开(公告)日：2014-08-12

申请号：US12215991

申请日：2008-06-30

申请人： Bernhard Sell ,  Oleg Golonzka

发明人： Bernhard Sell ,  Oleg Golonzka

IPC分类号： H01L21/02

CPC分类号： H01L23/535 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53266 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/4175 ,  H01L29/4925 ,  H01L29/66666 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an IID disposed on a top surface of a metal gate disposed on the substrate.

摘要翻译： 描述形成微电子器件的方法和相关结构。 这些方法可以包括形成包括设置在基板的源极/漏极接触件上的第一接触金属和设置在第一接触金属的顶表面上的第二接触金属的结构，其中第二接触金属设置在设置的IID内 在设置在基板上的金属栅极的顶面上。

公开(公告)号：US20120068180A1

公开(公告)日：2012-03-22

申请号：US13292865

申请日：2011-11-09

申请人： Rishabh Mehandru ,  Bernhard Sell ,  Anand Murthy ,  Lucian Shifren

发明人： Rishabh Mehandru ,  Bernhard Sell ,  Anand Murthy ,  Lucian Shifren

IPC分类号： H01L29/78

CPC分类号： H01L21/26513 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/76804 ,  H01L21/76814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7834

摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a tapered contact opening in an ILD disposed on a substrate, wherein a source/drain contact area is exposed, preamorphizing a portion of a source drain region of the substrate, implanting boron into the source/drain region through the tapered contact opening, forming a metal layer on the source/drain contact area, and then annealing the metal layer to form a metal silicide.

摘要翻译： 描述形成微电子器件的方法和相关结构。 这些方法可以包括在设置在衬底上的ILD中形成锥形接触开口，其中暴露源极/漏极接触区域，对基底的源极漏极区域的一部分进行预变质，通过锥形 接触开口，在源极/漏极接触区域上形成金属层，然后退火金属层以形成金属硅化物。

公开(公告)号：US07943469B2

公开(公告)日：2011-05-17

申请号：US11605739

申请日：2006-11-28

申请人： Ted E. Cook, Jr. ,  Bernhard Sell ,  Anand Murthy

发明人： Ted E. Cook, Jr. ,  Bernhard Sell ,  Anand Murthy

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/7834

摘要： A multi-component strain-inducing semiconductor region is described. In an embodiment, formation of such a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In one embodiment, the multi-component strain-inducing material region comprises a first portion and a second portion which are separated by an interface. In a specific embodiment, the concentration of charge-carrier dopant impurity atoms of the two portions are different from one another at the interface.

摘要翻译： 描述了多组分应变诱导半导体区域。 在一个实施方案中，在与晶体衬底横向相邻的这种应变诱导半导体区域的形成导致赋予晶体衬底的单轴应变，从而提供应变晶体衬底。 在一个实施例中，多组分应变诱导材料区域包括由界面分离的第一部分和第二部分。 在具体实施方案中，两部分的电荷 - 载流子掺杂剂杂质原子的浓度在界面处彼此不同。