公开(公告)号：US06797613B2

公开(公告)日：2004-09-28

申请号：US10196698

申请日：2002-07-16

申请人： Bernhard Sell ,  Annette Sänger ,  Georg Schulze-Icking

发明人： Bernhard Sell ,  Annette Sänger ,  Georg Schulze-Icking

IPC分类号： H01L21443

CPC分类号： H01L21/28556 ,  H01L21/28518

摘要： Tungsten silicide layers are formed on a substrate and a semiconductor component has deep trench capacitors with a filling of tungsten silicide. The tungsten silicide layers are deposited on the substrate at a temperature of less than 400° C. and at a pressure of less than 10 torr from the vapor phase. The vapor phase hs a tungsten-containing precursor substance and a silicon-containing precursor substance. The molar ratio of the silicon-containing precursor compound to the tungsten-containing precursor compound in the vapor phase is selected to be greater than 500.

摘要翻译： 在衬底上形成硅化钨层，并且半导体部件具有填充硅化钨的深沟槽电容器。 硅化钨层在低于400℃的温度和低于10托的压力下沉积在基底上。 气相hs是含钨前体物质和含硅前体物质。 气相中含硅前体化合物与含钨前体化合物的摩尔比选择为大于500。

公开(公告)号：US06916704B2

公开(公告)日：2005-07-12

申请号：US10167800

申请日：2002-06-12

申请人： Martin Gutsche ,  Bernhard Sell ,  Annette Sänger ,  Harald Seidl

发明人： Martin Gutsche ,  Bernhard Sell ,  Annette Sänger ,  Harald Seidl

IPC分类号： C23C14/58 ,  C23C16/56 ,  H01L21/20 ,  H01L21/302 ,  H01L21/3205 ,  H01L21/334 ,  H01L21/44 ,  H01L21/461 ,  H01L21/8242 ,  H01L29/94

CPC分类号： H01L29/66181 ,  H01L29/945

摘要： An upper capacitor electrode of a trench capacitor of a DRAM memory cell is formed at least in part as a result of a plurality of metal-containing layers being deposited one on top of another and in each case being conditioned after they have been deposited. In this way, the internal stress of the electrode layer can be reduced, and therefore a breaking strength and a resistance to leakage currents of the trench capacitor can be increased.

摘要翻译： 作为DRAM存储单元的沟槽电容器的上电容器电极，至少部分地由多个含金属层沉积在另一层之上而形成，并且在每种情况下在被沉积之后被调节。 以这种方式，可以减小电极层的内应力，因此可以提高沟槽电容器的断裂强度和耐漏电流。

公开(公告)号：US06774005B2

公开(公告)日：2004-08-10

申请号：US10206303

申请日：2002-07-26

申请人： Martin Gutsche ,  Peter Moll ,  Bernhard Sell ,  Annette Sänger ,  Harald Seidl

发明人： Martin Gutsche ,  Peter Moll ,  Bernhard Sell ,  Annette Sänger ,  Harald Seidl

IPC分类号： H01L218242

CPC分类号： H01L27/10861 ,  C23C16/32 ,  C23C16/45525 ,  C23C16/56 ,  H01L21/28556

摘要： At least a partial layer of an upper capacitor electrode is formed by metal carbide, preferably by a transition metal carbide. In one embodiment, the metal carbide layer is formed by depositing an alternating sequence of metal-containing layers and carbon-containing layers on top of one another and then subjecting them to a heat treatment, in such a manner that they mix with one another. The patterning of the layer sequence can be carried out before the carbide formation step.

摘要翻译： 上部电容器电极的至少一部分层由金属碳化物形成，优选由过渡金属碳化物形成。 在一个实施方案中，金属碳化物层通过在彼此顶部沉积含金属层和含碳层的交替序列形成，然后使它们以彼此混合的方式进行热处理。 层序列的图案化可以在碳化物形成步骤之前进行。

公开(公告)号：US07199414B2

公开(公告)日：2007-04-03

申请号：US10780075

申请日：2004-02-17

申请人： Matthias Goldbach ,  Bernhard Sell ,  Annette Sänger

发明人： Matthias Goldbach ,  Bernhard Sell ,  Annette Sänger

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/1087 ,  H01L27/10852 ,  H01L27/10861

摘要： The stress-reduced layer system has at least one first layer of polycrystalline or single-crystal semiconductor material, which adjoins a microcrystalline or amorphous, conducting or insulating second layer. The semiconductor layer is doped with at least two dopants of the same conductivity type, of which at least one is suitable for reducing mechanical stresses at the interface. The stress-reduced layer system, in a further embodiment, has at least one first layer of semiconductor material, conducting or insulating material and at least one conducting or insulating second layer. A further semiconductor layer, which is doped with at least one dopant that is suitable for reducing mechanical stresses at the interface between the second layer and the first layer, is arranged between the first layer and the second layer or it is applied to the surface of the first layer or the second layer that is opposite from the interface.

摘要翻译： 应力降低层系统具有至少一个第一层多晶或单晶半导体材料，其邻接微晶或非晶，导电或绝缘的第二层。 半导体层掺杂有至少两种相同导电类型的掺杂剂，其中至少一种适用于降低界面处的机械应力。 在另一实施例中，应力降低层系统具有至少一个第一半导体材料层，导电或绝缘材料以及至少一个导电或绝缘的第二层。 掺杂有至少一种适合于在第二层和第一层之间的界面处降低机械应力的掺杂剂的另一半导体层被布置在第一层和第二层之间，或者被施加到 与界面相对的第一层或第二层。

公开(公告)号：US06987295B2

公开(公告)日：2006-01-17

申请号：US10650817

申请日：2003-08-28

申请人： Bernhard Sell ,  Annette Sänger ,  Dirk Schumann

发明人： Bernhard Sell ,  Annette Sänger ,  Dirk Schumann

IPC分类号： H01L27/108

CPC分类号： H01L27/10861 ,  H01L27/1203

摘要： A trench capacitor for use in a DRAM memory cell contains a lower capacitor electrode, a storage dielectric, and an upper capacitor electrode, which are at least partially disposed in a trench. The lower capacitor electrode adjoins, in a lower trench region, a wall of the trench, while in the upper trench region there is a spacer layer that adjoins a wall of the trench and is made from an insulating material. The upper electrode contains at least three layers, a first layer disposed in the trench on the storage dielectric and containing doped polysilicon, a second layer disposed on the first layer and containing metal-silicide, and a third layer disposed on the second layer and containing doped polysilicon. The layers of the upper electrode in each case extending along the walls and the base of the trench up to at least the upper edge of the spacer layer.

摘要翻译： 用于DRAM存储单元的沟槽电容器包括至少部分地设置在沟槽中的下电容器电极，存储电介质和上电容器电极。 下部电容器电极在下部沟槽区域中邻接沟槽的壁，而在上部沟槽区域中存在间隔层，该间隔层邻接沟槽的壁并由绝缘材料制成。 上电极包含至少三层，第一层设置在存储电介质上的沟槽中并含有掺杂多晶硅，第二层设置在第一层上并含有金属硅化物，第三层设置在第二层上并含有 掺杂多晶硅。 每个壳体中的上电极的层沿着沟槽的壁和基底延伸到至少间隔层的上边缘。

公开(公告)号：US07129173B2

公开(公告)日：2006-10-31

申请号：US10649411

申请日：2003-08-27

申请人： Heike Drummer ,  Franz Kreupl ,  Annette Sänger ,  Manfred Engelhardt ,  Bernhard Sell ,  Peter Thieme

发明人： Heike Drummer ,  Franz Kreupl ,  Annette Sänger ,  Manfred Engelhardt ,  Bernhard Sell ,  Peter Thieme

IPC分类号： H01L21/302

CPC分类号： H01L21/31053 ,  H01L21/30625 ,  H01L21/31144 ,  H01L21/76819

摘要： A semiconductor substrate is provided, on which there is arranged a first layer, a second layer and a third layer. The third layer is, for example, a resist mask that is used to pattern the second layer. The second layer is, for example, a patterned hard mask used to pattern the first layer. Then, the third layer is removed and a fourth layer is deposited. The fourth layer is, for example, an insulator that fills the trenches which have been formed in the first layer. Then, the fourth layer is planarized by a CMP step. The planarization is continued and the second layer, which is, for example, a hard mask, is removed from the first layer together with the fourth layer. The fourth layer remains in place in a trench which is arranged in the first layer.

摘要翻译： 提供半导体衬底，其上布置有第一层，第二层和第三层。 第三层例如是用于图案化第二层的抗蚀剂掩模。 第二层例如是用于图案化第一层的图案化硬掩模。 然后，去除第三层，并沉积第四层。 第四层例如是填充已经形成在第一层中的沟槽的绝缘体。 然后，通过CMP步骤对第四层进行平面化。 继续进行平面化，并且第二层（例如硬掩模）与第四层一起从第一层去除。 第四层保持在布置在第一层中的沟槽中的适当位置。

公开(公告)号：US06998307B2

公开(公告)日：2006-02-14

申请号：US10650055

申请日：2003-08-26

申请人： Bernhard Sell ,  Annette Sänger ,  Dirk Schumann

发明人： Bernhard Sell ,  Annette Sänger ,  Dirk Schumann

IPC分类号： H01L21/8242

CPC分类号： H01L27/10861 ,  H01L21/28518 ,  H01L21/31604 ,  H01L27/10814 ,  H01L28/60

摘要： The present invention relates to a novel method for fabricating a storage capacitor designed as a trench or a stacked capacitor and is used in particular in a DRAM memory cell. The method includes steps of forming a lower, metallic capacitor electrode, a storage dielectric and an upper capacitor electrode. The lower, metallic capacitor electrode is formed in a self-aligned manner on a silicon base material in such a way that uncovered silicon regions are first produced at locations at which the lower capacitor electrode will be formed, and then metal silicide is selectively formed on the uncovered silicon regions.

公开(公告)号：US08941214B2

公开(公告)日：2015-01-27

申请号：US13995634

申请日：2011-12-22

申请人： Bernhard Sell

发明人： Bernhard Sell

IPC分类号： H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823431 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/823412 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7853

摘要： Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.

摘要翻译： 描述了半导体器件的半导体器件和形成具有不同宽度的半导体器件的方法。 例如，半导体器件包括设置在衬底上方的半导体本体。 栅电极堆叠设置在半导体本体的一部分上，以在栅电极堆叠下方限定半导体本体中的沟道区。 源极和漏极区域限定在栅电极堆叠的任一侧上的半导体本体中。 侧壁间隔件邻近栅极电极堆叠并且仅在源极和漏极区域的一部分上设置。 侧壁间隔物下方的源区和漏区的部分具有高于半导体本体的沟道区的高度和宽度的高度和宽度。

公开(公告)号：US20140252464A1

公开(公告)日：2014-09-11

申请号：US14284808

申请日：2014-05-22

申请人： Bernhard Sell ,  Oleg Golonzka

发明人： Bernhard Sell ,  Oleg Golonzka

IPC分类号： H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28

CPC分类号： H01L23/535 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53266 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/4175 ,  H01L29/4925 ,  H01L29/66666 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an IID disposed on a top surface of a metal gate disposed on the substrate.

摘要翻译： 描述形成微电子器件的方法和相关结构。 这些方法可以包括形成包括设置在基板的源极/漏极接触件上的第一接触金属和设置在第一接触金属的顶表面上的第二接触金属的结构，其中第二接触金属设置在设置的IID内 在设置在基板上的金属栅极的顶面上。

公开(公告)号：US07943992B2

公开(公告)日：2011-05-17

申请号：US12157556

申请日：2008-06-10

申请人： Bernhard Sell ,  Rishabh Mehandru

发明人： Bernhard Sell ,  Rishabh Mehandru

IPC分类号： H01L29/76

CPC分类号： H01L29/7834 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/66621

摘要： Methods and associated structures of forming a microelectronic device are described. Those structures may comprise a transistor comprising a metal gate disposed on a gate dielectric that is disposed on a substrate, and a source/drain region disposed adjacent a channel region of the transistor. The source/drain region comprises a source/drain extension comprising a vertex point, wherein a top surface of the channel region is substantially planar with the vertex point.

摘要翻译： 描述形成微电子器件的方法和相关结构。 这些结构可以包括晶体管，其包括设置在基板上的栅极电介质上的金属栅极和与晶体管的沟道区域相邻设置的源极/漏极区域。 源极/漏极区域包括源极/漏极延伸部分，其包括顶点，其中沟道区域的顶表面与顶点基本上是平面的。