公开(公告)号：US20090085065A1

公开(公告)日：2009-04-02

申请号：US12059907

申请日：2008-03-31

Applicant: Umesh K. Mishra ,  Lee S. McCarthy ,  Chang Soo Suh ,  Siddharth Rajan

Inventor： Umesh K. Mishra ,  Lee S. McCarthy ,  Chang Soo Suh ,  Siddharth Rajan

IPC: H01L29/778 ,  H01L21/18 ,  H01L21/20

CPC classification number: H01L29/66462 ,  H01L21/187 ,  H01L29/045 ,  H01L29/2003 ,  H01L29/7783

Abstract: A method for fabricating III-N semiconductor devices on the N-face of layers comprising (a) growing a III-nitride semiconductor device structure in a Ga-polar direction on a substrate, (b) attaching a Ga face of the III-nitride semiconductor device structure to a host substrate, and (c) removing the substrate to expose the N-face surface of the III-nitride semiconductor device structure. An N-polar (000-1) oriented III-nitride semiconductor device is also disclosed, comprising one or more (000-1) oriented nitride layers, each having an N-face opposite a group III-face, wherein at least one N-face is an at least partially exposed N-face, and a host substrate attached to one of the group III-faces.

Abstract translation: 一种用于在层的N面上制造III-N半导体器件的方法，包括（a）在衬底上生长Ga极性方向上的III族氮化物半导体器件结构，（b）将III族氮化物的Ga面 半导体器件结构，以及（c）去除衬底以露出III族氮化物半导体器件结构的N面。 还公开了一种N极（000-1）取向的III族氮化物半导体器件，其包括一个或多个（000-1）取向的氮化物层，每个具有与III族面相反的N面，其中至少一个N 表面是至少部分暴露的N面，以及附着到III组面中的一个的主体衬底。

公开(公告)号：US20080277682A1

公开(公告)日：2008-11-13

申请号：US12059918

申请日：2008-03-31

Applicant: Umesh K. Mishra ,  Michael Grundmann ,  Steven P. DenBaars ,  Shuji Nakamura

Inventor： Umesh K. Mishra ,  Michael Grundmann ,  Steven P. DenBaars ,  Shuji Nakamura

IPC: H01L33/00 ,  H01L21/00

CPC classification number: H01L33/22 ,  H01L33/04 ,  H01L33/32

Abstract: A light emitting diode, comprising a substrate, a buffer layer on the substrate, an active layer on the buffer layer and between an n-type layer and a p-type layer, a tunnel junction adjacent the p-type layer, and n-type contacts to the tunnel junction and the n-type layer, wherein the buffer layer, n-type layer, p-type layer, active region and tunnel junction comprise III-nitride material grown in a nitrogen-face (N-face) orientation. The substrate surface upon which the III-nitride material is deposited is patterned to provide embedded backside roughening. A top surface of the tunnel junction, which also the top surface of the III-nitride material, is roughened.

Abstract translation: 一种发光二极管，包括衬底，衬底上的缓冲层，缓冲层上的有源层，n型层和p型层之间，邻近p型层的隧道结，以及n型层， 类型接触到隧道结和n型层，其中缓冲层，n型层，p型层，有源区和隧道结包括以氮面（N面）取向生长的III族氮化物材料 。 图案化其上沉积有III族氮化物材料的衬底表面以提供嵌入式背面粗糙化。 隧道结的顶表面也是III族氮化物材料的顶表面被粗糙化。

公开(公告)号：US07091514B2

公开(公告)日：2006-08-15

申请号：US10413690

申请日：2003-04-15

Applicant: Michael D. Craven ,  Stacia Keller ,  Steven P. Denbaars ,  Tal Margalith ,  James Stephen Speck ,  Shuji Nakamura ,  Umesh K. Mishra

Inventor： Michael D. Craven ,  Stacia Keller ,  Steven P. Denbaars ,  Tal Margalith ,  James Stephen Speck ,  Shuji Nakamura ,  Umesh K. Mishra

IPC: H01L31/072

CPC classification number: C30B29/403 ,  C30B25/02 ,  C30B25/04 ,  C30B25/105 ,  C30B25/18 ,  C30B29/406 ,  C30B29/605 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647

Abstract: A method for forming non-polar (Al,B,In,Ga)N quantum well and heterostructure materials and devices. Non-polar (11{overscore (2)}0) a-plane GaN layers are grown on an r-plane (1{overscore (1)}02) sapphire substrate using MOCVD. These non-polar (11{overscore (2)}0) a-plane GaN layers comprise templates for producing non-polar (Al,B,In,Ga)N quantum well and heterostructure materials and devices.

Abstract translation: 一种形成非极性（Al，B，In，Ga）N量子阱和异质结构材料和器件的方法。 非极性（11（超（20））a面GaN层使用MOCVD在r平面（1（超芯（10 2））蓝宝石衬底上生长，这些非极性（11（超核（2O） 平面GaN层包括用于产生非极性（Al，B，In，Ga）N量子阱和异质结构材料和器件的模板。

公开(公告)号：US06825559B2

公开(公告)日：2004-11-30

申请号：US10335915

申请日：2003-01-02

Applicant: Umesh K. Mishra ,  Primit Parikh ,  Yifeng Wu

Inventor： Umesh K. Mishra ,  Primit Parikh ,  Yifeng Wu

IPC: H01L2900

CPC classification number: H05K1/0206 ,  H01L21/8252 ,  H01L23/147 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/66 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/7787 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/73253 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19105 ,  H01L2924/30105 ,  H05K1/181 ,  H05K2201/066 ,  Y10T29/4913 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A flip-chip integrated circuit includes a circuit substrate having electronic components. The circuit substrate typically includes GaAs or Si. Another substrate can include Group III nitride based active semiconductor devices. This substrate typically includes SiC and can be separated to provide individual nitride devices. After separation, one or more of the Group III devices can be flip-chip mounted onto the circuit substrate. The electronic components on the circuit substrate can be coupled to the nitride devices using conductive interconnects and/or vias.

Abstract translation: 倒装芯片集成电路包括具有电子部件的电路基板。 电路基板通常包括GaAs或Si。 另一个衬底可以包括基于III族氮化物的有源半导体器件。 该衬底通常包括SiC并且可以被分离以提供单独的氮化物器件。 分离后，III组器件中的一个或多个可以倒装芯片安装到电路基板上。 可以使用导电互连和/或通孔将电路基板上的电子部件耦合到氮化物器件。

公开(公告)号：US5084743A

公开(公告)日：1992-01-28

申请号：US494239

申请日：1990-03-15

Applicant: Umesh K. Mishra ,  Robert J. Trew

Inventor： Umesh K. Mishra ,  Robert J. Trew

IPC: H01L29/43 ,  H01L29/778 ,  H01L29/812

CPC classification number: H01L29/7783 ,  H01L29/432 ,  H01L29/812

Abstract: The gate voltage breakdown of an integrated circuit field effect transistor, especially a compound semiconductor metal semiconductor field effect transistor (MESFET) and high electron mobility transistor (HEMT) is dramatically increased by forming an electron trap layer on the surface of the device, under the gate contact and extending beyond the gate contact towards the drain contact. The electron trap layer is preferably a high resisitivity lattice matched monocrystalline layer having at least 10.sup.18 traps per cubic centimeter. For gallium arsenide based transistors, the electron trap layer is preferably formed by low temperature molecular beam epitaxy (MBE) of gallium and arsenic fluxes, to produce a monocrystalline gallium arsenide layer having 1% excess arsenic. For indium phosphide based transistors, the electron trap layer is preferably formed by low temperature MBE of aluminum, indium and arsenic fluxes to produce a monocrystalline aluminum indium arsenide layer having 1% excess arsenic.

Abstract translation: 集成电路场效应晶体管，特别是化合物半导体金属半导体场效应晶体管（MESFET）和高电子迁移率晶体管（HEMT）的栅极电压击穿通过在器件的表面上形成电子俘获层而显着增加， 栅极接触并延伸超过栅极接触到漏极接触。 电子捕获层优选是具有至少1018个陷阱/立方厘米的高电阻率晶格匹配单晶层。 对于基于砷化镓的晶体管，优选通过镓和砷通量的低温分子束外延（MBE）形成电子陷阱层，以产生具有1％过量砷的单晶砷化镓层。 对于基于磷化铟的晶体管，电子捕获层优选由铝，铟和砷通量的低温MBE形成，以产生具有1％过量砷的单晶铝砷化铟层。

公开(公告)号：US5077597A

公开(公告)日：1991-12-31

申请号：US568901

申请日：1990-08-17

Applicant: Umesh K. Mishra

Inventor： Umesh K. Mishra

IPC: H01J1/308

CPC classification number: B82Y15/00 ,  H01J1/308

Abstract: A planar doped barrier region of semiconductor material is coupled to a vacuum or gaseous region to provide electron emission from the planar doped barrier region into the vacuum or gaseous region. When a voltage is applied across the planar doped barrier region electrons flow from one end of the region to another. This flow results in the emission of electrons if the work function of the emission surface is less than the bandgap of the semiconductor material. The device of the present invention can be used as a vacuum microelectronic emitter, a vacuum microelectronic transistor, light source, klystron, or travelling wave tube.

Abstract translation: 半导体材料的平面掺杂阻挡区域耦合到真空或气体区域以提供从平面掺杂阻挡区域进入真空或气态区域的电子发射。 当跨平面掺杂阻挡区域施加电压时，电子从该区域的一端流向另一端。 如果发射表面的功函数小于半导体材料的带隙，则该流动导致电子的发射。 本发明的器件可以用作真空微电子发射器，真空微电子晶体管，光源，速调管或行波管。

公开(公告)号：US08686466B2

公开(公告)日：2014-04-01

申请号：US12953029

申请日：2010-11-23

Applicant: Robert M. Farrell, Jr. ,  Troy J. Baker ,  Arpan Chakraborty ,  Benjamin A. Haskell ,  P. Morgan Pattison ,  Rajat Sharma ,  Umesh K. Mishra ,  Steven P. DenBaars ,  James S. Speck ,  Shuji Nakamura

Inventor： Robert M. Farrell, Jr. ,  Troy J. Baker ,  Arpan Chakraborty ,  Benjamin A. Haskell ,  P. Morgan Pattison ,  Rajat Sharma ,  Umesh K. Mishra ,  Steven P. DenBaars ,  James S. Speck ,  Shuji Nakamura

IPC: H01L33/02

CPC classification number: H01L33/16 ,  B82Y20/00 ,  C30B23/025 ,  C30B25/18 ,  C30B29/403 ,  H01L21/02389 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02609 ,  H01L33/0004 ,  H01L33/0062 ,  H01L33/007 ,  H01L33/02 ,  H01S5/0422 ,  H01S5/2201 ,  H01S5/3202 ,  H01S5/34333 ,  H01S2304/04

Abstract: A method for growth and fabrication of semipolar (Ga, Al, In, B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation, growing a planar semipolar (Ga, Al, In, B)N template or nucleation layer on the substrate, and growing the semipolar (Ga, Al, In, B)N thin films, heterostructures or devices on the planar semipolar (Ga, Al, In, B)N template or nucleation layer. The method results in a large area of the semipolar (Ga, Al, In, B)N thin films, heterostructures, and devices being parallel to the substrate surface.

Abstract translation: 一种用于生长和制造半极性（Ga，Al，In，B）N薄膜，异质结构和器件的方法，包括鉴定特定器件应用的所需材料性质，基于所需材料性质选择半极性生长取向，选择 用于生长选择的半极性生长取向的合适底物，在衬底上生长平面半极性（Ga，Al，In，B）N模板或成核层，以及生长半极（Ga，Al，In，B）N薄膜 ，平面半极性（Ga，Al，In，B）N模板或成核层上的异质结构或器件。 该方法导致大面积的半极性（Ga，Al，In，B）N薄膜，异质结构和器件平行于衬底表面。

公开(公告)号：US08525230B2

公开(公告)日：2013-09-03

申请号：US12901988

申请日：2010-10-11

Applicant: Hugues Marchand ,  Brendan J. Moran ,  Umesh K. Mishra ,  James S. Speck

Inventor： Hugues Marchand ,  Brendan J. Moran ,  Umesh K. Mishra ,  James S. Speck

IPC: H01L29/737

CPC classification number: H01L23/562 ,  C30B25/02 ,  C30B29/403 ,  C30B29/406 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/0251 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/205 ,  H01L33/0025 ,  H01L33/0066 ,  H01L33/0075 ,  H01L33/12 ,  H01L33/32 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A field effect transistor including a compositionally graded group-III nitride layer on a silicon substrate.

Abstract translation: 一种场效应晶体管，包括在硅衬底上的III族氮化物层。

公开(公告)号：US08274206B2

公开(公告)日：2012-09-25

申请号：US13045148

申请日：2011-03-10

Applicant: Arpan Chakraborty ,  Likun Shen ,  Umesh K. Mishra

Inventor： Arpan Chakraborty ,  Likun Shen ,  Umesh K. Mishra

IPC: H01J1/62

CPC classification number: H01L25/0753 ,  F21K9/00 ,  H01L27/156 ,  H01L33/08 ,  H01L33/14 ,  H01L33/20 ,  H01L33/38 ,  H01L33/385 ,  H01L33/42 ,  H01L33/486 ,  H01L33/62 ,  H01L33/64 ,  H01L2924/0002 ,  H01L2933/0033 ,  H01L2933/0066 ,  H01L2924/00

Abstract: The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistances with improved current spreading and improved heat-sinking. Each pixel is a square with sides of dimension l. The series resistance is minimized by increasing the perimeter of an active region for the pixels. The series resistance is also minimized by shrinking the space between a mesa and n-contact for each pixel.

Abstract translation: 本发明公开了一种排列成阵列的多个交错像素，具有非常低的串联电阻，具有改进的电流扩散和改善的散热。 每个像素是具有尺寸l的边的正方形。 通过增加像素的有源区域的周长来使串联电阻最小化。 串联电阻也通过缩小每个像素的台面和n接触之间的空间来最小化。

公开(公告)号：US20120068191A1

公开(公告)日：2012-03-22

申请号：US13306763

申请日：2011-11-29

Applicant: Hugues Marchand ,  Brendan J. Moran ,  Umesh K. Mishra ,  James S. Speck

Inventor： Hugues Marchand ,  Brendan J. Moran ,  Umesh K. Mishra ,  James S. Speck

IPC: H01L33/32 ,  H01L29/267

CPC classification number: H01L23/562 ,  C30B25/02 ,  C30B29/403 ,  C30B29/406 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/0251 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/205 ,  H01L33/0025 ,  H01L33/0066 ,  H01L33/0075 ,  H01L33/12 ,  H01L33/32 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. A typical semiconductor film comprises a substrate and a graded gallium nitride layer deposited on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply.

Abstract translation: 公开了控制沉积在硅和碳化硅衬底上的GaN膜中的应力控制方法和由其制备的膜。 典型的方法包括提供衬底并在衬底上沉积梯度的氮化镓层，其具有基本上连续等级的从初始组成到由生长室中的至少一种前体的供应形成的最终组成的变化的组成，而不会中断 在供应。 典型的半导体膜包括沉积在衬底上的衬底和梯度的氮化镓层，其具有从初始组成到最终组成的基本连续等级的变化的组成，其由在生长室中供应至少一种前体而形成，而不会中断 在供应。