Abstract:
A coil structure includes a coil set including a first coil and a second coil. The first coil and the second coil are wound to form an annular area. A first end of the first coil and a first end of the second coil are close to an inner ring of the annular area. A second end of the first coil and a second end of the second coil are close to an outer ring of the annular area. The first end of the first coil is electrically connected to the first end of the second coil. A first projection-of the first coil on a plane perpendicular to an axial direction of the coil structure and a second projection of the second coil on the plane are mirror-symmetrical to each other.
Abstract:
An impedance match housing is described. The impedance match housing includes an impedance matching circuit having an input that is coupled to a radio frequency (RF) generator. The impedance matching circuit has an output that is coupled to a first RF strap. The impedance match housing includes a uniformity control circuit coupled in parallel to a portion of the first RF strap to modify uniformity in a processing rate of a substrate when the substrate is processed within a plasma chamber.
Abstract:
A method for ion-assisted etching a stack of alternating silicon oxide and silicon nitride layers in an etch chamber is provided. An etch gas comprising a fluorine component, helium, and a fluorohydrocarbon or hydrocarbon is flowed into the etch chamber. The gas is formed into an in-situ plasma in the etch chamber. A bias of about 10 to about 100 volts is provided to accelerate helium ions to the stack and activate a surface of the stack to form an activated surface for ion-assisted etching, wherein the in-situ plasma etches the activated surface of the stack.
Abstract:
The present disclosure relates to semiconductor manufacturing, in particular to a real-time method for qualifying the etch rate for plasma etch processes. A method for testing a semiconductor plasma etch chamber may include: depositing a film on a substrate of a wafer, the wafer including a center region and an edge region; depositing photoresist on top of the film in a pattern that isolates the center region from the edge region of the wafer; and performing an etch process on the wafer that includes at least three process steps. The three process steps may include: etching the film in any areas without photoresist covering the areas until a first clear endpoint signal is achieved; performing an in-situ ash to remove any photoresist; and etching the film in any areas exposed by the removal of the photoresist until a second clear endpoint is achieved. The method may further include determining whether both endpoints are achieved within respective previously set tolerances, and, if both endpoints are achieved within the previously set tolerance, qualifying the plasma etch chamber as verified.
Abstract:
A substrate support is provided, is configured to support a substrate in a plasma processing chamber, and includes first, second and third insulative layers, conduits and leads. The first insulative layer includes heater zones arranged in rows and columns. The second insulative layer includes conductive vias. First ends of the conductive vias are connected respectively to the heater zones. Second ends of the conductive vias are connected respectively to power supply lines. The third insulative layer includes power return lines. The conduits extend through the second insulative layer and into the third insulative layer. The leads extend through the conduits and connect to the heater zones. The heater zones are connected to the power return lines by the leads and are configured to heat corresponding portions of the substrate to provide a predetermined temperature profile across the substrate during processing of the substrate in the plasma processing chamber.
Abstract:
A heating plate for use in a substrate support is configured to provide temperature profile control of a substrate supported on the substrate support in a vacuum chamber of a substrate processing apparatus. The heating plate includes an independently controllable heater zones operable to tune a temperature profile on an upper surface of the heating plate. The heater zones are each powered by two or more power lines wherein each power line is electrically connected to a different group of the heater zones and each respective heater zone is electrically connected to a different pair of power lines.
Abstract:
The present disclosure generally comprises a heated showerhead assembly that may be used to supply processing gases into a processing chamber. The processing chamber may be an etching chamber. When processing gas is evacuated from the processing chamber, the uniform processing of the substrate may be difficult. As the processing gas is pulled away from the substrate and towards the vacuum pump, the plasma, in the case of etching, may not be uniform across the substrate. Uneven plasma may lead to uneven etching. To prevent uneven etching, the showerhead assembly may be separated into two zones each having independently controllable gas introduction and temperature control. The first zone corresponds to the perimeter of the substrate while the second zone corresponds to the center of the substrate. By independently controlling the temperature and the gas flow through the showerhead zones, etching uniformity of the substrate may be increased.
Abstract:
A substrate support in a semiconductor plasma processing apparatus, comprises multiple independently controllable thermal zones arranged in a scalable multiplexing layout, and electronics to independently control and power the thermal zones. A substrate support in which the substrate support is incorporated includes an electrostatic clamping electrode and a temperature controlled base plate. Methods for manufacturing the substrate support include bonding together ceramic or polymer sheets having thermal zones, power supply lines, power return lines and vias.
Abstract:
A gas-flow control method for a plasma apparatus is provided. The gas-flow control method includes mounting a first adjusting mechanism on a gas-distribution plate. The gas-distribution plate includes a number of exhaust openings, and the exhaust openings in a first area of the gas-distribution plate are masked by the first adjusting mechanism. The gas-flow control method also includes exhausting a gas from the exhaust openings in a first unmasked area of the gas-distribution plate, and the gas passing through the first adjusting mechanism into a plasma chamber. The gas-flow control method further includes generating an electric field to excite the gas in the plasma chamber into plasma.
Abstract:
Apparatus, methods, and computer programs for semiconductor processing in a capacitively-coupled plasma chamber are provided. A chamber includes a bottom radio frequency (RF) signal generator, a top RF signal generator, and an RF phase controller. The bottom RF signal generator is coupled to the bottom electrode in the chamber, and the top RF signal generator is coupled to the top electrode. Further, the bottom RF signal is set at a first phase, and the top RF signal is set at a second phase. The RF phase controller is operable to receive the bottom RF signal and operable to set the value of the second phase. Additionally, the RF phase controller is operable to track the first phase and the second phase to maintain a time difference between the maximum of the top RF signal and the minimum of the bottom RF signal at approximately a predetermined constant value, resulting in an increase of the negative ion flux to the surface of the wafer.