公开(公告)号：US20150325637A1

公开(公告)日：2015-11-12

申请号：US14796551

申请日：2015-07-10

申请人： SUMITOMO ELECTRIC INDUSTRIES, LTD.

发明人： Keiji ISHIBASHI

IPC分类号： H01L29/04 ,  H01L29/34 ,  H01L29/16 ,  H01L29/167 ,  C30B23/02 ,  C30B29/36

CPC分类号： H01L21/304 ,  C30B23/025 ,  C30B29/36 ,  C30B33/00 ,  H01L21/02002 ,  H01L21/02008 ,  H01L21/0201 ,  H01L21/02378 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02658 ,  H01L21/28 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/34 ,  H01L29/36 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7813 ,  Y10T428/21

摘要： A substrate capable of achieving a lowered probability of defects produced in a step of forming an epitaxial film or a semiconductor element, a semiconductor device including the substrate, and a method of manufacturing a semiconductor device are provided. A substrate is a substrate having a front surface and a back surface, in which at least a part of the front surface is composed of single crystal silicon carbide, the substrate having an average value of surface roughness Ra at the front surface not greater than 0.5 nm, a standard deviation σ of that surface roughness Ra not greater than 0.2 nm, an average value of surface roughness Ra at the back surface not smaller than 0.3 nm and not greater than 10 nm, standard deviation σ of that surface roughness Ra not greater than 3 nm, and a diameter D of the front surface not smaller than 110 mm.

公开(公告)号：US09159565B2

公开(公告)日：2015-10-13

申请号：US12544747

申请日：2009-08-20

申请人： Shyue Seng Tan ,  Lee Wee Teo ,  Ming Zhu

发明人： Shyue Seng Tan ,  Lee Wee Teo ,  Ming Zhu

IPC分类号： H01L29/76 ,  H01L21/336 ,  H01L21/265

CPC分类号： H01L21/26586 ,  H01L29/34 ,  H01L29/66356 ,  H01L29/7391

摘要： A method of manufacture of an integrated circuit system includes: providing a semiconductor substrate; implanting a well region, having a first conductivity, on the semiconductor substrate; patterning a gate oxide layer on the well region; implanting a source, having a second conductivity, at an angle for implanting under the gate oxide layer; selectively implanting a dopant pocket, having a third conductivity that is opposite the second conductivity, at the angle for forming the dopant pocket under the gate oxide layer; and implanting a drain, having the third conductivity, for forming a transistor channel asymmetrically positioned under the gate oxide layer.

摘要翻译： 一种集成电路系统的制造方法，包括：提供半导体衬底; 在所述半导体衬底上注入具有第一导电性的阱区; 在阱区上形成栅极氧化物层; 以一角度植入具有第二导电性的源，用于注入在栅极氧化物层下方; 选择性地注入具有与第二导电性相反的第三导电性的掺杂剂凹坑，以形成栅极氧化物层下面的掺杂剂口袋的角度; 以及注入具有第三导电性的漏极，以形成不对称地位于栅极氧化物层下方的晶体管沟道。

公开(公告)号：US09153646B2

公开(公告)日：2015-10-06

申请号：US13795339

申请日：2013-03-12

申请人： Kabushiki Kaisha Toshiba

发明人： Tatsuo Shimizu ,  Takashi Shinohe

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/10 ,  H01L29/167 ,  H01L21/04 ,  H01L29/32 ,  H01L29/34 ,  H01L29/739 ,  H01L29/94 ,  H01L29/08

CPC分类号： H01L29/1608 ,  H01L21/049 ,  H01L29/04 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/32 ,  H01L29/34 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7391 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7805 ,  H01L29/94

摘要： According to one embodiment, a semiconductor device includes a structural body, an insulating film, and a control electrode. The structural body has a first surface, and includes a first semiconductor region including silicon carbide of a first conductivity type, a second semiconductor region including silicon carbide of a second conductivity type, and a third semiconductor region including silicon carbide of the first conductivity type. The structural body has a portion in which the first semiconductor region, the second semiconductor region, and the third semiconductor region are arranged in this order in a first direction along the first surface. The insulating film is provided on the first surface of the structural body. The control electrode is provided on the insulating film. The structural body has a buried region provided between the second semiconductor region and the first surface. The buried region is doped with a group V element.

摘要翻译： 根据一个实施例，半导体器件包括结构体，绝缘膜和控制电极。 结构体具有第一表面，并且包括第一半导体区域，其包括第一导电类型的碳化硅，第二半导体区域，包括第二导电类型的碳化硅，第三半导体区域包括第一导电类型的碳化硅。 结构体具有第一半导体区域，第二半导体区域和第三半导体区域沿着第一表面沿第一方向依次布置的部分。 绝缘膜设置在结构体的第一表面上。 控制电极设置在绝缘膜上。 结构体具有设置在第二半导体区域和第一表面之间的掩埋区域。 掩埋区域掺杂有V族元素。

公开(公告)号：US09147731B2

公开(公告)日：2015-09-29

申请号：US13925339

申请日：2013-06-24

申请人： Sumitomo Electric Industries, Ltd.

发明人： Toru Hiyoshi ,  Kosuke Uchida ,  Takeyoshi Masuda

IPC分类号： H01L21/20 ,  H01L29/15 ,  H01L29/16 ,  H01L21/263 ,  H01L21/04 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/34 ,  H01L29/04

CPC分类号： H01L29/1608 ,  H01L21/0445 ,  H01L21/049 ,  H01L21/2636 ,  H01L21/324 ,  H01L29/045 ,  H01L29/34 ,  H01L29/51 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7802

摘要： A method for manufacturing a silicon carbide semiconductor device includes the following steps. A silicon carbide substrate is prepared. A first heating step of heating the silicon carbide substrate in an atmosphere of oxygen is performed. A second heating step of heating the silicon carbide substrate to a temperature of 1300° C. or more and 1500° C. or less in an atmosphere of gas containing nitrogen atoms or phosphorus atoms is performed after the first heating step. A third heating step of heating the silicon carbide substrate in an atmosphere of a first inert gas is performed after the second heating step. Thus, the silicon carbide semiconductor device in which threshold voltage variation is small, and a method for manufacturing the same can be provided.

摘要翻译： 一种制造碳化硅半导体器件的方法包括以下步骤。 制备碳化硅衬底。 执行在氧气气氛中加热碳化硅衬底的第一加热步骤。 在第一加热步骤之后，在含有氮原子或磷原子的气体气氛中，将碳化硅基板加热至1300℃以上且1500℃以下的温度的第二加热工序。 在第二加热步骤之后进行在第一惰性气体气氛中加热碳化硅衬底的第三加热步骤。 因此，可以提供阈值电压变化小的碳化硅半导体器件及其制造方法。

公开(公告)号：US09117830B2

公开(公告)日：2015-08-25

申请号：US14296519

申请日：2014-06-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Hao Hsu ,  Chia-Chen Chen ,  Tzung-Chi Fu ,  Tzu-Wei Kao ,  Yu Chao Lin

IPC分类号： H01L23/00 ,  H01L29/06 ,  H01L29/34 ,  H01L21/3215 ,  G03F7/20 ,  H01L21/265 ,  H01L21/683

CPC分类号： H01L23/562 ,  G03F7/70708 ,  H01L21/26506 ,  H01L21/32155 ,  H01L21/6831 ,  H01L29/0603 ,  H01L29/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a front surface and a backside surface; integrated circuit features formed on the front surface of the semiconductor substrate; and a polycrystalline silicon layer disposed on the backside surface of the semiconductor substrate.

摘要翻译： 本公开提供了半导体结构的一个实施例。 半导体结构包括具有前表面和后表面的半导体衬底; 集成电路特征形成在半导体衬底的前表面上; 以及设置在半导体衬底的背面上的多晶硅层。

公开(公告)号：US20150187936A1

公开(公告)日：2015-07-02

申请号：US14659902

申请日：2015-03-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Chang CHENG ,  Ruey-Hsin LIU

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L21/265 ,  H01L29/66 ,  H01L29/417 ,  H01L29/40

CPC分类号： H01L29/41766 ,  H01L21/26513 ,  H01L21/26586 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/34 ,  H01L29/66712 ,  H01L29/7809 ,  H01L29/78624

摘要： A semiconductor device includes a buried layer in a substrate, the buried layer having a first dopant type. The semiconductor device further includes a first layer over the buried layer, the first layer having the first dopant type. The semiconductor device further includes at least one first well in the first layer, the at least one first well having a second dopant type. The semiconductor device further includes an implantation region in a sidewall of the first layer, the implantation region having the second dopant type, wherein the implantation region is below the at least one first well. The semiconductor device further includes a metal electrode extending from the buried layer to a drain contact, wherein the metal electrode is insulated from the first layer and the at least one first well by an insulation layer.

摘要翻译： 半导体器件包括衬底中的掩埋层，该掩埋层具有第一掺杂剂型。 半导体器件还包括在掩埋层上的第一层，第一层具有第一掺杂剂类型。 所述半导体器件还包括所述第一层中的至少一个第一阱，所述至少一个第一阱具有第二掺杂剂类型。 所述半导体器件还包括在所述第一层的侧壁中的注入区域，所述注入区域具有所述第二掺杂剂类型，其中所述注入区域在所述至少一个第一阱之下。 半导体器件还包括从掩埋层延伸到漏极接触的金属电极，其中金属电极通过绝缘层与第一层和至少一个第一阱绝缘。

公开(公告)号：US09064836B1

公开(公告)日：2015-06-23

申请号：US12852643

申请日：2010-08-09

申请人： Chin-Tien Chiu ,  Shrikar Bhagath ,  Yuang Zhang ,  Lu Zhong ,  Kaiyou Qian

发明人： Chin-Tien Chiu ,  Shrikar Bhagath ,  Yuang Zhang ,  Lu Zhong ,  Kaiyou Qian

IPC分类号： H01L29/34 ,  H01L21/02

CPC分类号： H01L29/34 ,  B24B7/228 ,  B24B37/107 ,  H01L21/02024 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/3221 ,  H01L25/065 ,  H01L2224/48091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A semiconductor wafer, die and semiconductor package formed therefrom are disclosed, where the inactive surface of the wafer has an extrinsic gettering pattern formed from a texturing process. In examples, the texturing process follows a polishing process that removes stress concentration point from the inactive surface of the wafer.

摘要翻译： 公开了从其形成的半导体晶片，管芯和半导体封装，其中晶片的非活性表面具有由纹理化工艺形成的外在吸气图案。 在实例中，纹理化处理遵循从晶片的非活性表面去除应力集中点的抛光工艺。

公开(公告)号：US20150147861A1

公开(公告)日：2015-05-28

申请号：US14543820

申请日：2014-11-17

申请人： JAEYOUNG PARK ,  SUNGHO KANG ,  KICHUL KIM ,  Sunyoung LEE ,  HAN KI LEE ,  BONYOUNG KOO

发明人： JAEYOUNG PARK ,  SUNGHO KANG ,  KICHUL KIM ,  Sunyoung LEE ,  HAN KI LEE ,  BONYOUNG KOO

IPC分类号： H01L21/3065 ,  H01L21/762 ,  H01L29/66

CPC分类号： H01L27/0886 ,  H01L21/0206 ,  H01L21/302 ,  H01L21/306 ,  H01L21/32053 ,  H01L21/76224 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/34 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795

摘要： A method of manufacturing a semiconductor device includes forming a first plurality of recessed regions in a substrate, the substrate having a protruded active region between the first plurality of recessed regions and the protruded active region having an upper surface and a sidewall, forming a device isolation film in the first plurality of recessed regions, the device isolation film exposing the upper surface and an upper portion of the sidewall of the protruded active region, and performing a first plasma treatment on the exposed surface of the protruded active region, wherein the plasma treatment is performed using a plasma gas containing at least one of an inert gas and a hydrogen gas in a temperature of less than or equal to about 700.

摘要翻译： 一种制造半导体器件的方法包括在衬底中形成第一多个凹陷区域，所述衬底在所述第一多个凹陷区域之间具有突出的有源区域和所述突出的有源区域具有上表面和侧壁，形成器件隔离 在所述第一多个凹陷区域中的膜，所述器件隔离膜暴露所述突出的有源区的所述上表面和所述侧壁的上部，并且对所述突出的有源区的所述暴露表面进行第一等离子体处理，其中所述等离子体处理 使用包含惰性气体和氢气中的至少一种的等离子体气体在小于或等于约700℃的温度下进行。

公开(公告)号：US20150061088A1

公开(公告)日：2015-03-05

申请号：US14207880

申请日：2014-03-13

申请人： Dong-soo LEE ,  Myoung-Jae LEE ,  Seong-ho CHO ,  Mohammad Rakib Uddin ,  David SEO ,  Moon-seung YANG ,  Sang-moon LEE ,  Sung-hun LEE ,  Ji-hyun HUR ,  Eui-chul HWANG

发明人： Dong-soo LEE ,  Myoung-Jae LEE ,  Seong-ho CHO ,  Mohammad Rakib Uddin ,  David SEO ,  Moon-seung YANG ,  Sang-moon LEE ,  Sung-hun LEE ,  Ji-hyun HUR ,  Eui-chul HWANG

IPC分类号： H01L29/20 ,  H01L21/322

CPC分类号： H01L29/34 ,  H01L21/02175 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/022 ,  H01L21/02304 ,  H01L21/28158 ,  H01L21/28264 ,  H01L21/322 ,  H01L21/3228 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66522 ,  H01L29/7851

摘要： The present disclosure relates to a semiconductor device including an oxygen gettering layer between a group III-V compound semiconductor layer and a dielectric layer, and a method of fabricating the semiconductor device. The semiconductor device may include a compound semiconductor layer; a dielectric layer disposed on the compound semiconductor layer; and an oxygen gettering layer interposed between the compound semiconductor layer and the dielectric layer. The oxygen gettering layer includes a material having a higher oxygen affinity than a material of the compound semiconductor layer.

摘要翻译： 本公开内容涉及包括III-V族化合物半导体层和电介质层之间的吸氧层的半导体器件以及制造该半导体器件的方法。 半导体器件可以包括化合物半导体层; 设置在所述化合物半导体层上的电介质层; 以及置于化合物半导体层和电介质层之间的吸氧层。 吸氧层包括具有比化合物半导体层的材料更高的氧亲合力的材料。

公开(公告)号：US08933487B2

公开(公告)日：2015-01-13

申请号：US14063207

申请日：2013-10-25

申请人： HRL Laboratories, LLC

发明人： Sameh G. Khalil ,  Karim S. Boutros

IPC分类号： H01L29/66 ,  H01L29/34 ,  H01L29/778 ,  H01L21/265 ,  H01L29/423 ,  H01L29/20

CPC分类号： H01L29/66431 ,  H01L21/26546 ,  H01L29/2003 ,  H01L29/34 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786

摘要： A high electron mobility field effect transistor (HEMT) includes a two dimensional electron gas (2DEG) in the drift region between the gate and the drain that has a non-uniform lateral 2DEG distribution that increases in a direction in the drift region from the gate to the drain.

摘要翻译： 高电子迁移率场效应晶体管（HEMT）包括栅极和漏极之间的漂移区域中的二维电子气体（2DEG），其具有在栅极和漏极的漂移区域中的方向上增加的非均匀横向2DEG分布 到排水