公开(公告)号：US11825665B2

公开(公告)日：2023-11-21

申请号：US17949436

申请日：2022-09-21

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC分类号： H01L29/78 ,  H10B99/00 ,  H01L27/105 ,  H01L27/12 ,  H10B12/00 ,  H10B41/20 ,  H10B41/70 ,  H01L29/24 ,  H01L29/786 ,  G11C13/00 ,  H01L49/02 ,  H10B10/00

CPC分类号： H10B99/00 ,  H01L27/105 ,  H01L27/124 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/7869 ,  H01L29/78696 ,  H10B12/00 ,  H10B41/20 ,  H10B41/70 ,  G11C13/003 ,  G11C13/0007 ,  G11C2213/79 ,  H01L28/40 ,  H10B10/00

摘要： An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which stored data can be stored even when power is not supplied in a data storing time and there is no limitation on the number of times of writing. The semiconductor device includes a first transistor which includes a first channel formation region using a semiconductor material other than an oxide semiconductor, a second transistor which includes a second channel formation region using an oxide semiconductor material, and a capacitor. One of a second source electrode and a second drain electrode of the second transistor is electrically connected to one electrode of the capacitor.

公开(公告)号：US20230343388A1

公开(公告)日：2023-10-26

申请号：US18340214

申请日：2023-06-23

申请人： SK hynix Inc.

发明人： Nam Jae LEE

IPC分类号： G11C11/413

CPC分类号： G11C11/413 ,  H10B10/00

摘要： There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a source layer; a channel structure extending in a first direction from within the source layer; a source-channel contact layer surrounding the channel structure on the source layer; a first select gate layer overlapping with the source-channel contact layer and surrounding the channel structure; a stack including interlayer insulating layers and conductive patterns that are alternately stacked in the first direction and surrounding the channel structure, the stack overlapping with the first select gate layer; and a first insulating pattern that is formed thicker between the first select gate layer and the channel structure than between the stack and the channel structure.

公开(公告)号：US20230307283A1

公开(公告)日：2023-09-28

申请号：US18200387

申请日：2023-05-22

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC分类号： H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40

CPC分类号： H01L21/6835 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  G11C8/16 ,  H10B10/00 ,  H10B10/125 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B12/053 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L2924/13062 ,  H01L23/3677

摘要： A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming at least one second level above the second metal layer; performing a first lithography step on the second level; forming a third level on top of the second level; performing processing steps to form first memory cells within the second level and form second memory cells within the third level, where the first memory cells include at least one second transistor, and the second memory cells include at least one third transistor; and then at performing at least one deposition step which deposits gate electrodes for both the second and the third transistors, and forming at least four independent memory arrays.

公开(公告)号：US11705189B2

公开(公告)日：2023-07-18

申请号：US17473648

申请日：2021-09-13

申请人： SK hynix Inc.

发明人： Nam Jae Lee

IPC分类号： H01L27/115 ,  G11C11/413 ,  H10B10/00

CPC分类号： G11C11/413 ,  H10B10/00

摘要： There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a source layer; a channel structure extending in a first direction from within the source layer; a source-channel contact layer surrounding the channel structure on the source layer; a first select gate layer overlapping with the source-channel contact layer and surrounding the channel structure; a stack including interlayer insulating layers and conductive patterns that are alternately stacked in the first direction and surrounding the channel structure, the stack overlapping with the first select gate layer; and a first insulating pattern that is formed thicker between the first select gate layer and the channel structure than between the stack and the channel structure.

公开(公告)号：US11646309B2

公开(公告)日：2023-05-09

申请号：US17827705

申请日：2022-05-28

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Brian Cronquist

IPC分类号： H01L27/06 ,  G03F9/00 ,  H01L21/762 ,  H01L21/84 ,  H01L23/48 ,  H01L23/544 ,  H01L27/02 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/66 ,  H01L29/45 ,  H01L29/786 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/812 ,  H01L29/423 ,  H01L29/732 ,  H01L29/808 ,  H01L21/768 ,  H01L21/822 ,  H01L23/367 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/00 ,  H01L21/268 ,  H01L27/088

CPC分类号： H01L27/0688 ,  G03F9/7076 ,  G03F9/7084 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823871 ,  H01L21/84 ,  H01L23/367 ,  H01L23/481 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/458 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66848 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/78639 ,  H01L29/78642 ,  H01L29/78645 ,  H01L29/808 ,  H01L29/812 ,  H10B10/00 ,  H10B10/125 ,  H10B12/053 ,  H10B12/09 ,  H10B12/50 ,  H10B20/00 ,  H10B41/20 ,  H10B43/20 ,  H01L21/268 ,  H01L24/73 ,  H01L27/088 ,  H01L29/66545 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025

摘要： A semiconductor device including: a first silicon level including a first single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first silicon level; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 40 nm alignment error; a via disposed through the second level, where each of the second transistors includes a metal gate, where a typical thickness of the second metal layer is greater than a typical thickness of the third metal layer by at least 50%.

公开(公告)号：US20240347375A1

公开(公告)日：2024-10-17

申请号：US18135350

申请日：2023-04-17

申请人： NANYA TECHNOLOGY CORPORATION

发明人： KUO-CHUNG HSU ,  EN-JUI LI

IPC分类号： H01L21/762

CPC分类号： H01L21/76224 ,  H10B10/00 ,  H10B12/00 ,  H10B20/25

摘要： A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate having an active region and a shallow trench isolation (STI) adjacent to the active region of the substrate. The STI includes a charge trapping layer and a liner disposed between the charge trapping layer and the active region of the substrate, wherein the charge trapping layer is doped with an impurity.

公开(公告)号：US12117935B2

公开(公告)日：2024-10-15

申请号：US17852300

申请日：2022-06-28

申请人： Advanced Micro Devices, Inc.

发明人： Chintan S. Patel ,  Vydhyanathan Kalyanasundharam ,  Benjamin Tsien ,  Alexander J. Branover

IPC分类号： G06F12/00 ,  G06F12/0802

CPC分类号： G06F12/0802 ,  G06F2212/60 ,  G06F13/00 ,  H10B10/00 ,  H10B12/00

摘要： A technique for operating a cache is disclosed. The technique includes utilizing a first portion of a cache in a directly accessed manner; and utilizing a second portion of the cache as a cache.

公开(公告)号：US20240321346A1

公开(公告)日：2024-09-26

申请号：US18582183

申请日：2024-02-20

申请人： Shanghai Huali Integrated Circuit Corporation

发明人： Mu CAO ,  Koichi KUROKI

IPC分类号： G11C11/413 ,  H10B10/00

CPC分类号： G11C11/413 ,  H10B10/00

摘要： The present application discloses a static random-access memory. Upon an entry to a sleep mode, a power switch transistor in a word line drive power supply module is off, thus controlling the elimination of a leakage path of a word line driver, so that leakage power consumption of the SRAM is maintained at that of an on standby state of a normal operating mode or a data retention mode. The entry to and exit from the sleep mode of the SRAM can be carried out flexibly and quickly, without complying with strict timing requirements required by stepwise powering-on and stepwise powering-off, thereby facilitating the implementation of a leakage control function without increasing a layout size. The present application discloses an integrated circuit layout of the static random-access memory.

公开(公告)号：US20240282365A1

公开(公告)日：2024-08-22

申请号：US18653585

申请日：2024-05-02

申请人： SK hynix Inc.

发明人： Nam Jae LEE

IPC分类号： G11C11/413 ,  H10B10/00

CPC分类号： G11C11/413 ,  H10B10/00

摘要： There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a source layer; a channel structure extending in a first direction from within the source layer; a source-channel contact layer surrounding the channel structure on the source layer; a first select gate layer overlapping with the source-channel contact layer and surrounding the channel structure; a stack including interlayer insulating layers and conductive patterns that are alternately stacked in the first direction and surrounding the channel structure, the stack overlapping with the first select gate layer; and a first insulating pattern that is formed thicker between the first select gate layer and the channel structure than between the stack and the channel structure.

公开(公告)号：US20240281497A1

公开(公告)日：2024-08-22

申请号：US18444406

申请日：2024-02-16

申请人： Rain Neuromorphics Inc.

发明人： Jack David Kendall ,  Mohammed Elneanaei Abdelmoneem Fouda

IPC分类号： G06F17/16 ,  H10B10/00

CPC分类号： G06F17/16 ,  H10B10/00

摘要： A resistive cell is described. The resistive cell includes static random access memory (SRAM) cells, a digital-to-analog converter (DAC), and a transistor network. The SRAM cells have a multi-bit state. The DAC converts the multi-bit state to an analog signal. The transistor network receives the analog signal as an input and provides a digitally controlled conductance. The resistive cell is integrated into a matrix multiplication network.