公开(公告)号：US20170047425A1

公开(公告)日：2017-02-16

申请号：US14826803

申请日：2015-08-14

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporations ,  STMicroelectronics, Inc.

Inventor： Steven BENTLEY ,  Jody FRONHEISER ,  Xin MIAO ,  Joseph WASHINGTON ,  Pierre MORIN

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L29/06 ,  H01L21/324

CPC classification number: H01L29/66537 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/324 ,  H01L29/0638 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/165

Abstract: A method of performing an early PTS implant and forming a buffer layer under a bulk or fin channel to control doping in the channel and the resulting bulk or fin device are provided. Embodiments include forming a recess in a substrate; forming a PTS layer below a bottom surface of the recess; forming a buffer layer on the bottom surface and on side surfaces of the recess; forming a channel layer on and adjacent to the buffer layer; and annealing the channel, buffer, and PTS layers.

Abstract translation: 提供了一种执行早期PTS植入和在体或鳍通道下形成缓冲层以控制沟道中的掺杂并且产生的体或鳍器件的方法。 实施例包括在基板中形成凹部; 在所述凹部的底表面下方形成PTS层; 在所述凹部的底表面和侧表面上形成缓冲层; 在缓冲层上和邻近缓冲层上形成沟道层; 并对通道，缓冲器和PTS层进行退火。

公开(公告)号：US09570512B2

公开(公告)日：2017-02-14

申请号：US14960595

申请日：2015-12-07

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John Hongguang Zhang

IPC: H01L21/4763 ,  H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2436 ,  H01L23/528 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1633 ,  H01L45/1691

Abstract: A resistive random access memory (RRAM) structure is formed on a supporting substrate and includes a first electrode and a second electrode. The first electrode is made of a silicided fin on the supporting substrate and a first metal liner layer covering the silicided fin. A layer of dielectric material having a configurable resistive property covers at least a portion of the first metal liner. The second electrode is made of a second metal liner layer covering the layer of dielectric material and a metal fill in contact with the second metal liner layer. A non-volatile memory cell includes the RRAM structure electrically connected between an access transistor and a bit line.

Abstract translation: 在支撑衬底上形成电阻随机存取存储器（RRAM）结构，并且包括第一电极和第二电极。 第一电极由支撑衬底上的硅化物翅片和覆盖硅化物翅片的第一金属衬垫层制成。 具有可配置电阻性能的电介质材料层覆盖第一金属衬垫的至少一部分。 第二电极由覆盖电介质材料层的第二金属衬垫层和与第二金属衬垫层接触的金属填充物制成。 非易失性存储单元包括电连接在存取晶体管和位线之间的RRAM结构。

公开(公告)号：US20170031007A1

公开(公告)日：2017-02-02

申请号：US14809384

申请日：2015-07-27

Applicant: STMicroelectronics, Inc. ,  STMicroelectronics (Research & Development) Limited

Inventor： Darin K. Winterton ,  Sam Lee

IPC: G01S7/486

CPC classification number: G01S7/4861 ,  G01S7/4802 ,  G01S17/08

Abstract: An electronic device includes a ranging light source and a reflected light detector. A logic circuit causes the ranging light source to emit ranging light at a target. Reflected light from the target is detected using the reflected light detector, with the reflected light being a portion of the ranging light that reflects from the target back toward the reflected light detector. An intensity of the reflected light is determined using the reflected light detector. A distance to the target is determined based upon time elapsed between activating the ranging light source and detecting the reflected ranging light. Reflectance of the target is calculated, based upon the intensity of the reflected light and the distance to the target.

Abstract translation: 电子装置包括测距光源和反射光检测器。 逻辑电路使得测距光源在目标上发射测光。 使用反射光检测器检测来自目标的反射光，其中反射光是从目标反射到反射光检测器的测距光的一部分。 使用反射光检测器确定反射光的强度。 基于激活测距光源和检测反射的测光灯之间的时间来确定到目标​​的距离。 基于反射光的强度和与目标的距离，计算目标的反射率。

公开(公告)号：US09554324B2

公开(公告)日：2017-01-24

申请号：US14051583

申请日：2013-10-11

Applicant: STMicroelectronics, Inc.

Inventor： Liwen Chu ,  George A. Vlantis

IPC: H04W40/24 ,  H04W48/16 ,  H04W8/00 ,  H04W48/12

CPC classification number: H04W48/16 ,  H04W8/005 ,  H04W40/244 ,  H04W40/246 ,  H04W48/12

Abstract: A wireless network access point generates a fast initial link setup (FILS) discovery frame for broadcast to one or more wireless stations. The wireless network access point supports many operating channels including a primary channel. The FILS discovery frame includes a data field populated with an identification of a channel number for that primary channel of the wireless network access point. The FILS discovery frame includes another data field populated with a primary channel operating class identification. The broadcast FILS discovery frame further includes data indicating whether indicating whether multiple BSSIDs are supported. An FD capability field of the FILS discovery frame includes sub-fields indicating one or more of operation channel width, PHY type of the wireless access point, number of spatial streams supported by the wireless access point and multiple BSSIDs support provided by the wireless access point.

Abstract translation: 无线网络接入点生成用于广播到一个或多个无线站的快速初始链路建立（FILS）发现帧。 无线网络接入点支持许多操作信道，包括主信道。 FILS发现帧包括填充有无线网络接入点的主信道的信道号的标识的数据字段。 FILS发现帧包括填充有主信道操作类标识的另一数据字段。 广播FILS发现帧还包括指示是否指示是否支持多个BSSID的数据。 FILS发现帧的FD能力字段包括指示操作信道宽度，无线接入点的PHY类型，无线接入点支持的空闲数量的数量和由无线接入点提供的多个BSSID支持中的一个或多个的子字段 。

公开(公告)号：US09548361B1

公开(公告)日：2017-01-17

申请号：US14755663

申请日：2015-06-30

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Pierre Morin

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L29/161

CPC classification number: H01L29/785 ,  H01L27/0886 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/41791 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7849 ,  H01L2029/7858

Abstract: A self-aligned SiGe FinFET device features a relaxed channel region having a high germanium concentration. Instead of first introducing germanium into the channel and then attempting to relax the resulting strained film, a relaxed channel is formed initially to accept the germanium. In this way, a presence of germanium can be established without straining or damaging the lattice. Gate structures are patterned relative to intrinsic silicon fins, to ensure that the gates are properly aligned, prior to introducing germanium into the fin lattice structure. After aligning the gate structures, the silicon fins are segmented to elastically relax the silicon lattice. Then, germanium is introduced into the relaxed silicon lattice, to produce a SiGe channel that is substantially stress-free and also defect-free. Using the method described, concentration of germanium achieved in a structurally stable film can be increased to a level greater than 85%.

Abstract translation: 自对准SiGe FinFET器件具有具有高锗浓度的松弛沟道区。 不是首先将锗引入通道，然后尝试松弛所得到的应变膜，最初形成松弛的通道以接受锗。 以这种方式，可以建立锗的存在而不会使晶格变形或损坏。 在将锗引入鳍状晶格结构之前，门结构相对于本征硅散热片图案化，以确保栅极正确对准。 在对齐栅极结构之后，将硅片段分段以弹性地松弛硅晶格。 然后，将锗引入松弛的硅晶格中，以产生基本上无应力且也无缺陷的SiGe沟道。 使用所述方法，在结构稳定的膜中实现的锗的浓度可以增加到大于85％的水平。

公开(公告)号：US09543214B2

公开(公告)日：2017-01-10

申请号：US14526081

申请日：2014-10-28

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics, Inc.

Inventor： Denis Rideau ,  Elise Baylac ,  Emmanuel Josse ,  Pierre Morin ,  Olivier Nier

IPC: H01L21/8234 ,  H01L21/84 ,  H01L21/762 ,  H01L29/78 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3115 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/324 ,  H01L27/12

CPC classification number: H01L21/823481 ,  H01L21/02356 ,  H01L21/02532 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/3081 ,  H01L21/3105 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/76237 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/7831 ,  H01L29/7846 ,  H01L29/7847

Abstract: The invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a semiconductor structure having a stressed semiconductor layer, one or more first isolation trenches in a first direction for delimiting a first dimension of at least one transistor to be formed in said semiconductor structure; forming, in the semiconductor structure, one or more second isolation trenches in a second direction for delimiting a second dimension of the at least one transistor, the first and second isolation trenches being at least partially filled with an insulating material; and before or after the formation of the second isolation trenches, decreasing the viscosity of the insulating material in the first isolation trenches by implanting atoms of a first material into the first isolation trenches, wherein atoms of the first material are not implanted into the second isolation trenches.

Abstract translation: 本发明涉及一种形成具有单轴应力的半导体层的方法，包括：在具有应力半导体层的半导体结构中形成在第一方向上的一个或多个第一隔离沟槽，以限定待形成的至少一个晶体管的第一维度 在所述半导体结构中; 在所述半导体结构中，在第二方向上形成用于限定所述至少一个晶体管的第二尺寸的一个或多个第二隔离沟槽，所述第一和第二隔离沟槽至少部分地填充有绝缘材料; 并且在形成第二隔离沟槽之前或之后，通过将第一材料的原子注入到第一隔离沟槽中来降低第一隔离沟槽中的绝缘材料的粘度，其中第一材料的原子未被注入第二隔离层 沟渠

公开(公告)号：US20170005106A1

公开(公告)日：2017-01-05

申请号：US15191359

申请日：2016-06-23

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L27/115 ,  H01L29/423 ,  H01L27/06 ,  H01L29/08 ,  H01L23/538 ,  H01L27/02 ,  H01L29/786 ,  H01L29/66 ,  H01L29/788 ,  H01L29/06 ,  H01L27/07

CPC classification number: H01L23/5386 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823871 ,  H01L21/823885 ,  H01L23/5384 ,  H01L27/0255 ,  H01L27/0688 ,  H01L27/0705 ,  H01L27/0727 ,  H01L27/092 ,  H01L27/11582 ,  H01L29/0676 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78696 ,  H01L29/7926

Abstract: A modular interconnect structure facilitates building complex, yet compact, integrated circuits from vertical GAA FETs. The modular interconnect structure includes annular metal contacts to the transistor terminals, sectors of stacked discs extending radially outward from the vertical nanowires, and vias in the form of rods. Extension tabs mounted onto the radial sector interconnects permit signals to fan out from each transistor terminal. Adjacent interconnects are linked by linear segments. Unlike conventional integrated circuits, the modular interconnects as described herein are formed at the same time as the transistors. Vertical GAA NAND and NOR gates provide building blocks for creating all types of logic gates to carry out any desired Boolean logic function. Stacked vertical GAA FETs are made possible by the modular interconnect structure. The modular interconnect structure permits a variety of specialized vertical GAA devices to be integrated on a silicon substrate using standard CMOS processes.

Abstract translation: 模块化互连结构有助于从垂直GAA FET构建复杂而紧凑的集成电路。 模块化互连结构包括到晶体管端子的环形金属触点，从垂直纳米线径向向外延伸的堆叠盘的扇区，以及棒形式的通孔。 安装在径向扇形互连上的延伸片允许信号从每个晶体管端子扇出。 相邻互连由线性段链接。 与常规集成电路不同，如本文所述的模块化互连在晶体管的同时形成。 垂直GAA NAND和NOR门提供构建块，用于创建所有类型的逻辑门，以执行任何所需的布尔逻辑功能。 堆叠的垂直GAA FET通过模块化互连结构成为可能。 模块化互连结构允许使用标准CMOS工艺将各种专用垂直GAA器件集成在硅衬底上。

公开(公告)号：US20170005009A1

公开(公告)日：2017-01-05

申请号：US14754812

申请日：2015-06-30

Applicant: STMicroelectronics, Inc.

Inventor： John C. Pritiskutch ,  Richard Hildenbrandt

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823493 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/324 ,  H01L21/823412 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/7827

Abstract: First and second transistors with different electrical characteristics are supported by a substrate having a first-type dopant. The first transistor includes a well region within the substrate having the first-type dopant, a first body region within the well region having a second-type dopant and a first source region within the first body region and laterally offset from the well region by a first channel. The second transistor includes a second body region within the semiconductor substrate layer having the second-type dopant and a second source region within the second body region and laterally offset from material of the substrate by a second channel having a length greater than the length of the first channel. A gate region extends over portions of the first and second body regions for the first and second channels, respectively.

Abstract translation: 具有不同电特性的第一和第二晶体管由具有第一种掺杂剂的衬底支撑。 所述第一晶体管包括在所述衬底内具有所述第一类型掺杂剂的阱区域，所述阱区域内的第一体区域具有第二类型掺杂物和所述第一体区域内的第一源极区域并且沿着所述阱区域横向偏移 第一频道 第二晶体管包括具有第二类型掺杂剂的半导体衬底层内的第二体区域，以及在第二体区内的第二源极区域，并且通过第二通道横向偏离衬底的材料，第二沟道的长度大于 第一频道 栅极区域分别在第一和第二通道的第一和第二主体区域的部分上延伸。

公开(公告)号：US09538525B2

公开(公告)日：2017-01-03

申请号：US14148047

申请日：2014-01-06

Applicant: STMicroelectronics, Inc.

Inventor： Liwen Chu ,  George A. Vlantis

IPC: H04W74/04 ,  H04W72/00 ,  H04W72/04 ,  H04L12/43

CPC classification number: H04W72/0446 ,  H04L12/43 ,  H04W72/005 ,  H04W74/04

Abstract: Methods and apparatus for implementing a robust unicast/broadcast/multicast protocol are provided. In one aspect, a method of avoiding collision of intra-basic service set unicast, broadcast or multicast transmissions notifies stations in the basic service set of a reserved transmit opportunity for a unicast, broadcast or multicast transmission. Transmissions from at least one station in the basic service set are deferred until after the reserved unicast, broadcast or multicast transmit opportunity.

Abstract translation: 提供了用于实现鲁棒的单播/广播/多播协议的方法和装置。 在一个方面，避免基本内部服务设置单播，广播或多播传输的冲突的方法通知用于单播，广播或多播传输的预留发送机会的基本服务集中的站。 基本服务集中的至少一个站的传输延迟到保留的单播，广播或多播发送机会之后。

公开(公告)号：US20160380118A1

公开(公告)日：2016-12-29

申请号：US15260206

申请日：2016-09-08

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing LIU ,  John H. ZHANG

IPC: H01L29/84 ,  H01L21/306 ,  H01L21/02 ,  H01H49/00 ,  H01H59/00

CPC classification number: H01L29/84 ,  B82B3/00 ,  H01H1/0094 ,  H01H49/00 ,  H01H50/005 ,  H01H59/0009 ,  H01H2001/0084 ,  H01L21/02532 ,  H01L21/30608

Abstract: An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position. Such motion of the cantilever breaks the circuit, restoring a void underneath the gate that blocks current flow, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. By doping the cantilever and using a back bias and a metallic cantilever tip, sensitivity of the switch can be further improved. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 μm2.

Abstract translation: 纳米级机电开关形式的集成晶体管消除了CMOS电流泄漏并提高了开关速度。 纳米尺度的机电开关具有从衬底的一部分延伸到空腔中的半导体悬臂。 悬臂响应于施加到晶体管栅极的电压而弯曲，从而在栅极下形成导电沟道。 当设备关闭时，悬臂返回到其静止位置。 悬臂的这种运动打破了电路，恢复了阻挡电流的门下方的空隙，从而解决了泄漏问题。 纳米机电开关的制造与现有的CMOS晶体管制造工艺兼容。 通过掺杂悬臂并使用背偏压和金属悬臂尖，可以进一步提高开关的灵敏度。 纳米机电开关的占地面积可以小至0.1×0.1μm2。