公开(公告)号：US09419111B2

公开(公告)日：2016-08-16

申请号：US14748270

申请日：2015-06-24

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  Prasanna Khare ,  Nicolas Loubet

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/78 ,  H01L29/08 ,  H01L21/265 ,  H01L29/417 ,  H01L21/225

CPC classification number: H01L27/0886 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.

公开(公告)号：US09418900B1

公开(公告)日：2016-08-16

申请号：US14800290

申请日：2015-07-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc.

Inventor： Hong He ,  Nicolas Loubet ,  James Kuss ,  Junli Wang

IPC: H01L21/8238

CPC classification number: H01L21/845 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/823821 ,  H01L21/823857 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/161

Abstract: A method for forming fins includes growing a SiGe layer and a silicon layer over a surface of a bulk Si substrate, patterning fin structures from the silicon layer and the SiGe layer and filling between the fin structures with a dielectric fill. Trenches are formed to expose end portions of the fin structures. A first region of the fin structures is blocked off. The SiGe layer of the fin structures of a second region is removed by selectively etching the fin structures from the end portions to form voids, which are filled with dielectric material. The silicon layer of the fin structures is exposed. The SiGe layer in the first region is thermally oxidized to drive Ge into the silicon layer to form SiGe fins on an oxide layer in the first region and silicon fins on the dielectric material in the second region.

Abstract translation: 用于形成翅片的方法包括在体Si衬底的表面上生长SiGe层和硅层，从硅层和SiGe层图案化翅片结构，并用电介质填充物填充翅片结构。 形成沟槽以暴露翅片结构的端部。 翅片结构的第一个区域被阻挡。 通过从端部选择性地蚀刻翅片结构来去除第二区域的翅片结构的SiGe层，以形成填充有电介质材料的空隙。 翅片结构的硅层被暴露。 第一区域中的SiGe层被热氧化以将Ge驱动到硅层中，以在第一区域中的氧化物层上形成SiGe散热片，并在第二区域中在介电材料上形成硅散热片。

公开(公告)号：US09406751B2

公开(公告)日：2016-08-02

申请号：US14296818

申请日：2014-06-05

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-chen Yeh

IPC: H01L29/08 ,  H01L27/12 ,  H01L29/786 ,  H01L21/84 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/786 ,  H01L29/78684

Abstract: A method for making a semiconductor device is provided. Raised source and drain regions are formed with a tensile strain-inducing material, after thermal treatment to form source drain extension regions, to thereby preserve the strain-inducing material in desired substitutional states.

Abstract translation: 提供一种制造半导体器件的方法。 在热处理之后，用拉伸应变诱导材料形成凸起的源极和漏极区域以形成源极漏极延伸区域，从而将应变诱导材料保持在期望的替代状态。

公开(公告)号：US20160211171A1

公开(公告)日：2016-07-21

申请号：US15081749

申请日：2016-03-25

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Qing Liu ,  Shom Ponoth

IPC: H01L21/762 ,  H01L21/311 ,  H01L21/84

CPC classification number: H01L21/76283 ,  H01L21/31111 ,  H01L21/76232 ,  H01L21/84

Abstract: Isolation trenches are etched through an active silicon layer overlying a buried oxide on a substrate into the substrate, and through any pad dielectric(s) on the active silicon layer. Lateral epitaxial growth of the active silicon layer forms protrusions into the isolation trenches to a lateral distance of at least about 5 nanometers, and portions of the isolation trenches around the protrusions are filled with dielectric. Raised source/drain regions are formed on portions of the active silicon layer including a dielectric. As a result, misaligned contacts passing around edges of the raised source/drain regions remain spaced apart from sidewalls of the substrate in the isolation trenches.

Abstract translation: 通过将衬底上的掩埋氧化物覆盖在衬底中以及通过有源硅层上的任何焊盘电介质的有源硅层蚀刻隔离沟槽。 有源硅层的横向外延生长在隔离沟槽中形成至少约5纳米的横向距离的突起，并且围绕突起的部分隔离沟槽被电介质填充。 在包括电介质的有源硅层的部分上形成凸起的源极/漏极区。 结果，穿过凸起的源极/漏极区域的边缘的不对准触点保持与隔离沟槽中的衬底的侧壁间隔开。

公开(公告)号：US20160211155A1

公开(公告)日：2016-07-21

申请号：US15085678

申请日：2016-03-30

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L21/67 ,  H01L21/677

CPC classification number: H01L21/3212 ,  B24B37/005 ,  H01L21/02074 ,  H01L21/6704 ,  H01L21/67207 ,  H01L21/67219 ,  H01L21/67253 ,  H01L21/67706 ,  H01L22/14 ,  H01L22/20

Abstract: CMP selectivity, removal rate, and uniformity are controlled both locally and globally by altering electric charge at the wafer surface. Surface charge characterization is performed by an on-board metrology module. Based on a charge profile map, the wafer can be treated in an immersion bath to impart a more positive or negative charge overall, or to neutralize the entire wafer before the CMP operation is performed. If charge hot spots are detected on the wafer, a charge pencil can be used to neutralize localized areas. One type of charge pencil bears a tapered porous polymer tip that is placed in close proximity to the wafer surface. Films present on the wafer absorb ions from, or surrender ions to, the charge pencil tip, by electrostatic forces. The charge pencil can be incorporated into a CMP system to provide an in-situ treatment prior to the planarization step or the slurry removal step.

公开(公告)号：US09385195B1

公开(公告)日：2016-07-05

申请号：US14675536

申请日：2015-03-31

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. Zhang

IPC: H01L29/745 ,  H01L27/148 ,  H01L21/00 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L29/10 ,  H01L29/49 ,  H01L29/20 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L27/10879 ,  B82Y10/00 ,  H01L21/28008 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823885 ,  H01L21/823892 ,  H01L27/0814 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/0653 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/66909 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/7855 ,  H01L29/7856 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696 ,  H01L31/0392 ,  H01L33/04 ,  H01L45/1233 ,  H01L2029/7858

Abstract: A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.

Abstract translation: 垂直隧道FET（TFET）为关键尺寸低于7nm的晶体管提供低功耗，高速开关性能。 垂直TFET使用全栅（GAA）器件结构，其具有在形成于硅衬底中的掺杂阱的表面上方延伸的圆柱形结构。 圆柱形结构包括从掺杂阱外延生长的下部漏极区域，沟道和上部源极区域。 该通道由本征硅制成，而源极和漏极区域原位掺杂。 环形栅极围绕通道，电容性地控制从所有侧面通过通道的电流。 源极可以通过前侧触点电接触，而漏极通过背面触点进行访问，该触点提供低接触电阻并且还用作散热器。 垂直TFET集成电路的可靠性通过将垂直TFET耦合到静电放电（ESD）二极管来增强。

公开(公告)号：US09385078B1

公开(公告)日：2016-07-05

申请号：US15064688

申请日：2016-03-09

Applicant: International Business Machines Corporation ,  Tokyo Electron Limited ,  STMicroelectronics, Inc.

Inventor： Yannick Feurprier ,  Joe Lee ,  Lars W. Liebmann ,  Yann Mignot ,  Terry A. Spooner ,  Douglas M. Trickett ,  Mehmet Yilmaz

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/0332 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a via in an integrated circuit comprises patterning a first opening in a first hardmask, the first hardmask disposed on a first organic self-planarizing polymer (OPL) layer, removing an exposed portion of the first OPL layer to define a cavity, removing an exposed portion of a second hardmask in the cavity, removing an exposed portion of a first dielectric layer disposed under the second hardmask to further define the cavity, removing an exposed portion of a first cap layer in the cavity, removing an exposed portion of a second dielectric layer to further define the cavity, removing an exposed portion of a second cap layer to further define the cavity, removing an exposed portion of a liner layer over a second conductive material in the cavity, and depositing a conductive material in the cavity.

公开(公告)号：US20160191058A1

公开(公告)日：2016-06-30

申请号：US14985887

申请日：2015-12-31

Applicant: STMicroelectronics, Inc.

Inventor： Chetan BISHT ,  Harry SCRIVENER, III

IPC: H03K19/0175 ,  H01L23/50 ,  H01L27/02 ,  H01L23/528

CPC classification number: H03K19/017509 ,  G06F17/5072 ,  G06F17/5077 ,  H01L23/50 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit system-on-chip (SOC) includes a semiconductor substrate, a plurality of components made up of transistors formed in the substrate, and a plurality of interconnection lines providing electrical connectivity among the components. Use of a channel-less design eliminates interconnection channels on the top surface of the chip. Instead, interconnection lines are abutted to one another in a top layer of metallization, thus preserving 5-10% of chip real estate. Clock buffers that are typically positioned along interconnection channels between components are instead located within regions of the substrate that contain the components. Design rules for channel-less integrated circuits permit feed-through interconnections and exclude multi-fanout interconnections.

公开(公告)号：US20160190322A1

公开(公告)日：2016-06-30

申请号：US14584639

申请日：2014-12-29

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, Inc.

Inventor： Qing LIU ,  Ruilong XIE ,  Xiuyu CAI ,  Chun-chen YEH

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/45 ,  H01L21/02 ,  H01L29/417 ,  H01L29/08

CPC classification number: H01L29/7851 ,  H01L21/02181 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795

Abstract: A large area electrical contact for use in integrated circuits features a non-planar, sloped bottom profile. The sloped bottom profile provides a larger electrical contact area, thus reducing the contact resistance, while maintaining a small contact footprint. The sloped bottom profile can be formed by recessing an underlying layer, wherein the bottom profile can be crafted to have a V-shape, U-shape, crescent shape, or other profile shape that includes at least a substantially sloped portion in the vertical direction. In one embodiment, the underlying layer is an epitaxial fin of a FinFET. A method of fabricating the low-resistance electrical contact employs a thin etch stop liner for use as a hard mask. The etch stop liner, e.g., HfO2, prevents erosion of an adjacent gate structure during the formation of the contact.

Abstract translation: 用于集成电路的大面积电接触具有非平面，倾斜的底部轮廓。 倾斜的底部轮廓提供更大的电接触面积，从而降低接触电阻，同时保持小的接触足迹。 倾斜的底部轮廓可以通过凹陷下面的层来形成，其中底部轮廓可以被制造成具有V形，U形，月牙形或其它轮廓形状，其在竖直方向上至少包括基本上倾斜的部分 。 在一个实施例中，下层是FinFET的外延翅片。 制造低电阻电接触的方法采用用作硬掩模的薄蚀刻停止衬垫。 蚀刻停止衬垫，例如HfO 2，防止在形成接触期间相邻栅极结构的侵蚀。

公开(公告)号：US20160190315A1

公开(公告)日：2016-06-30

申请号：US14587849

申请日：2014-12-31

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Qing LIU ,  Thomas SKOTNICKI

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7838 ,  H01L21/28114 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7834

Abstract: An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material. A gate dielectric is positioned on a top surface and on the exposed side surface of the second layer of semiconductor material. A gate electrode is positioned on the top surface and the exposed side surface of the second layer of semiconductor material.