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    Method and system for internal layer-layer thermal enhancement
    52.
    发明授权
    Method and system for internal layer-layer thermal enhancement 有权
    内层热增强方法和系统

    公开(公告)号：US08367478B2

    公开(公告)日：2013-02-05

    申请号：US13151672

    申请日：2011-06-02

    Applicant: Gerald K. Bartley ,  Charles L. Johnson ,  John E. Kelly, III ,  David R. Motschman

    Inventor： Gerald K. Bartley ,  Charles L. Johnson ,  John E. Kelly, III ,  David R. Motschman

    IPC: H01L21/50 ,  H01L21/48 ,  H01L23/34 ,  H01L23/52 ,  H01L23/48 ,  H01L23/40 ,  H01L23/538

    CPC classification number: H01L29/0657 ,  H01L23/3677 ,  H01L23/4275 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589

    Abstract: The exemplary embodiments of the present invention provide a method and apparatus for enhancing the cooling of a chip stack of semiconductor chips. The method includes creating a first chip with circuitry on a first side and creating a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The method further includes creating a cavity in a second side of the first chip between the connectors and filling the cavity with a thermal material. The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes wherein portions of a second side of the first chip between the connectors is removed to provide a cavity in which a thermal material is placed.

    Abstract translation: 本发明的示例性实施例提供了一种用于增强半导体芯片的芯片堆叠的冷却的方法和装置。 该方法包括在第一侧上创建具有电路的第一芯片，并通过连接器网格将第二芯片电连接并机械耦合到第一芯片。 该方法还包括在连接器之间的第一芯片的第二侧中形成空腔，并用热材料填充空腔。 具有增强的冷却装置的半导体芯片的芯片堆叠包括具有第一侧上的电路的第一芯片和通过连接器格栅电和机械地耦合到第一芯片的第二芯片。 该装置还包括：其中，连接器之间的第一芯片的第二侧的部分被去除以提供放置热材料的空腔。

    Resistance sensing for defeating microchip exploitation
    53.
    发明授权
    Resistance sensing for defeating microchip exploitation 失效
    用于击败微芯片开发的电阻感测

    公开(公告)号：US08214657B2

    公开(公告)日：2012-07-03

    申请号：US12181387

    申请日：2008-07-29

    Applicant: Gerald K Bartley ,  Darryl J Becker ,  Paul E Dahlen ,  Philip R Germann ,  Andrew B Maki ,  Mark O Maxson ,  John E. Sheets, II

    Inventor： Gerald K Bartley ,  Darryl J Becker ,  Paul E Dahlen ,  Philip R Germann ,  Andrew B Maki ,  Mark O Maxson ,  John E. Sheets, II

    IPC: G06F11/30

    CPC classification number: G06F21/755 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2224/0401

    Abstract: A method, program product and apparatus include resistance structures positioned proximate security sensitive microchip circuitry. Alteration in the position, makeup or arrangement of the resistance structures may be detected and initiate an action for defending against a reverse engineering or other exploitation effort. The resistance structures may be automatically and selectively designated for monitoring. Some of the resistance structures may have different resistivities. The sensed resistance may be compared to an expected resistance, ratio or other resistance-related value. The structures may be intermingled with false structures, and may be overlapped or otherwise arranged relative to one another to further complicate unwelcome analysis.

    Abstract translation: 一种方法，程序产品和装置包括位于安全敏感的微芯片电路附近的电阻结构。 可以检测抵抗结构的位置，构成或布置的变化，并启动防止逆向工程或其他开发工作的动作。 电阻结构可以自动和选择性地指定用于监测。 一些电阻结构可能具有不同的电阻率。 感测的电阻可以与期望的电阻，比率或其他电阻相关值进行比较。 结构可能与假结构混合，并且可以相对于彼此重叠或以其它方式布置，以进一步使不受欢迎的分析复杂化。

    Universal Inter-Layer Interconnect for Multi-Layer Semiconductor Stacks
    57.
    发明申请
    Universal Inter-Layer Interconnect for Multi-Layer Semiconductor Stacks 有权
    多层半导体堆叠的通用层间互连

    公开(公告)号：US20100271071A1

    公开(公告)日：2010-10-28

    申请号：US12431259

    申请日：2009-04-28

    Applicant: Gerald K. Bartley ,  Russell Dean Hoover ,  Charles Luther Johnson ,  Steven Paul VanderWiel ,  Patrick Ronald Varekamp

    Inventor： Gerald K. Bartley ,  Russell Dean Hoover ,  Charles Luther Johnson ,  Steven Paul VanderWiel ,  Patrick Ronald Varekamp

    IPC: H01L25/00 ,  G06F17/50

    CPC classification number: G06F17/5068 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01087 ,  H01L2224/05599 ,  H01L2224/05099

    Abstract: A circuit arrangement and method utilize a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers. Based upon a standardized placement of the inter-layer interface region in each circuit layer, and a standardized arrangement of electrical conductors associated with the inter-layer bus, each circuit layer may designed using a standardized template upon which the design features necessary to implement the inter-layer bus are already provided, thereby simplifying circuit layer design and the interconnection of functional units to the inter-layer bus. In addition, vertically-oriented supernodes may be defined within a semiconductor stack to provide multiple independently-operating nodes having functional units disposed in multiple circuit layers of the stack.

    Abstract translation: 电路布置和方法利用多层半导体堆叠中的通用的标准化层间互连，以便于布置在半导体管芯堆叠上的功能单元之间的互连和通信。 多层半导体堆叠中的每个电路层需要包括布置在基本上相同的地形位置处的层间界面区域，使得当将这样的电路层设置在其上的半导体管芯堆叠在一起时，电气 布置在每个半导体管芯内的导体彼此对准以提供相对于各个电路层垂直或横向取向的层间总线。 基于每个电路层中的层间界面区域的标准化布置以及与层间总线相关联的电导体的标准化布置，每个电路层可以使用标准化模板来设计，在该模板上设计实现 已经提供了层间总线，从而简化了电路层设计和功能单元与层间总线的互连。 此外，可以在半导体堆叠内定义垂直取向的超节点，以提供多个独立运行的节点，其具有布置在堆叠的多个电路层中的功能单元。

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