公开(公告)号：US09754921B2

公开(公告)日：2017-09-05

申请号：US14683195

申请日：2015-04-10

Applicant: Ki-Tae Park ,  Kang-Wook Lee ,  Young-Don Choi ,  Yun-Sang Lee

Inventor： Ki-Tae Park ,  Kang-Wook Lee ,  Young-Don Choi ,  Yun-Sang Lee

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/64 ,  G11C5/06 ,  H01L23/34 ,  H01L23/538

CPC classification number: H01L25/0657 ,  G11C5/06 ,  H01L23/34 ,  H01L23/5384 ,  H01L23/64 ,  H01L24/17 ,  H01L2224/16 ,  H01L2224/1712 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2225/1058 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/19106 ,  H01L2924/00

Abstract: A stacked semiconductor apparatus and method of fabricating same are disclosed. The apparatus includes upper and lower semiconductor devices having a similar pattern of connection elements. When stacked connected the resulting plurality of semiconductor devices includes a serial connection path traversing the stack, and may also include parallel connection paths, back-side mounted large components, and vertical thermal conduits.

公开(公告)号：US09393633B2

公开(公告)日：2016-07-19

申请号：US12551960

申请日：2009-09-01

Applicant: Pascal P Blais ,  Paul F Fortier ,  Kang-Wook Lee ,  Jae-Woong Nah ,  Soojae Park ,  Robert L Toutant ,  Alain A Warren

Inventor： Pascal P Blais ,  Paul F Fortier ,  Kang-Wook Lee ,  Jae-Woong Nah ,  Soojae Park ,  Robert L Toutant ,  Alain A Warren

IPC: B23K20/00 ,  B23K1/00 ,  H01L21/56 ,  H01L23/00

CPC classification number: B23K1/0016 ,  H01L21/563 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/73204 ,  H01L2224/75704 ,  H01L2224/75985 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15787 ,  H01L2924/3511 ,  H01L2924/01026 ,  H01L2924/00

Abstract: A method and apparatus for making chip assemblies is disclosed that prevent or reduce the cracking and delamination of ultra low-k dielectrics in the back-end-of-line in Si chips that can occur during the chip assembly process. The method and apparatus apply pressure to the top and bottom surfaces of a substrate during the chip bonding process so that the bending and warping of the assembled modules are reduced. The reduced bending and warping prevent or reduce the cracking and delamination of ultra low-k dielectrics.

Abstract translation: 公开了一种用于制造芯片组件的方法和装置，其防止或减少在芯片组装过程中可能发生的Si芯片中后端的超低k电介质的开裂和分层。 该方法和装置在芯片接合过程期间对基板的顶表面和底表面施加压力，使得组装的模块的弯曲和翘曲减小。 减少弯曲和翘曲防止或减少超低k电介质的开裂和分层。

公开(公告)号：US09030004B2

公开(公告)日：2015-05-12

申请号：US13659146

申请日：2012-10-24

Applicant: Ki-Tae Park ,  Kang-Wook Lee ,  Young-Don Choi ,  Yun-Sang Lee

Inventor： Ki-Tae Park ,  Kang-Wook Lee ,  Young-Don Choi ,  Yun-Sang Lee

IPC: H01L23/538 ,  H01L23/34 ,  H01L23/64 ,  H01L25/065 ,  G11C5/06

CPC classification number: H01L25/0657 ,  G11C5/06 ,  H01L23/34 ,  H01L23/5384 ,  H01L23/64 ,  H01L24/17 ,  H01L2224/16 ,  H01L2224/1712 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2225/1058 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/19106 ,  H01L2924/00

Abstract: A stacked semiconductor apparatus and method of fabricating same are disclosed. The apparatus includes upper and lower semiconductor devices having a similar pattern of connection elements. When stacked connected the resulting plurality of semiconductor devices includes a serial connection path traversing the stack, and may also include parallel connection paths, back-side mounted large components, and vertical thermal conduits.

Abstract translation: 公开了一种叠层半导体器件及其制造方法。 该装置包括具有相似图形的连接元件的上半导体器件和下半导体器件。 当堆叠连接时，所得到的多个半导体器件包括穿过堆叠的串行连接路径，并且还可以包括并联连接路径，背面安装的大部件和垂直热导管。

公开(公告)号：US08629059B2

公开(公告)日：2014-01-14

申请号：US12969977

申请日：2010-12-16

Applicant: Ho-Jin Lee ,  Kang-Wook Lee ,  Myeong-Soon Park ,  Ju-il Choi ,  Son-Kwan Hwang

Inventor： Ho-Jin Lee ,  Kang-Wook Lee ,  Myeong-Soon Park ,  Ju-il Choi ,  Son-Kwan Hwang

IPC: H01L23/48

CPC classification number: H01L23/528 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/00012

Abstract: Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.

Abstract translation: 形成集成电路器件的方法包括在半导体衬底的第一表面上形成层间电介质层，然后形成延伸穿过层间电介质层并进入半导体衬底的互连孔。 第一侧壁间隔层形成在互连孔的侧壁上。 在互连孔的底部的半导体衬底被各向同性蚀刻以在半导体衬底中限定底切凹部。 该蚀刻步骤使用第一侧壁间隔层作为蚀刻掩模进行。 然后用通孔电极填充互连孔和未切割凹部。 去除半导体衬底的第二表面足够的持续时间以露出包含通孔电极的未切割凹部。

公开(公告)号：US08444774B2

公开(公告)日：2013-05-21

申请号：US12731369

申请日：2010-03-25

Applicant: Eric Duschesne ,  Kang-Wook Lee ,  Valerie Oberson

Inventor： Eric Duschesne ,  Kang-Wook Lee ,  Valerie Oberson

IPC: B23K35/34

CPC classification number: B23K35/362 ,  Y10T428/12493

Abstract: The invention relates to a composition of matter comprising a soldering flux, wherein the flux consists essentially of a combination of a fluxing agent and a solvent, and wherein the fluxing agent comprises a keto acid such as levulinic acid or acetylbutyric acid. The flux may also comprises an ester acid, or comprises a mixture of the keto acid with the ester acid. The solvent comprises a mixture of a tacky solvent with a non-tacky solvent. The invention also relates to a process comprising soldering at least two surfaces together, each of which comprises a metal area to which solder can adhere by employing the following steps in any order: applying solder to at least one of the metal areas, aligning the metal areas so that they are superimposed over one another, heating at least one of the areas to a temperature that comprises at least the melting temperature of the solder. The last step comprises joining the superimposed areas to one another. The process employs the flux composition operatively associated with the solder, and in one embodiment the invention comprises a mixture of the flux composition with powdered solder. In another embodiment, the process comprises IMS, C4 and C4NP processes and the solder comprises a lead free solder. The invention also comprises a product produced by the foregoing process or processes.

Abstract translation: 本发明涉及包含助焊剂的物质组合物，其中助熔剂基本上由助熔剂和溶剂的组合组成，并且其中助熔剂包括酮酸，例如乙酰丙酸或乙酰基丁酸。 助熔剂还可以包含酯酸，或包含酮酸与酯酸的混合物。 溶剂包括粘性溶剂与非粘性溶剂的混合物。 本发明还涉及一种方法，其包括将至少两个表面焊接在一起，每个表面包括金属区域，焊料可以以任何顺序通过以下步骤粘附到该金属区域：将焊料施加到至少一个金属区域，使金属对准 区域，使得它们彼此叠加，将至少一个区域加热至至少包括焊料的熔化温度的温度。 最后一步包括将叠加的区域相互连接。 该方法使用与焊料可操作地相关联的助熔剂组合物，并且在一个实施方案中，本发明包括焊剂组合物与粉末焊料的混合物。 在另一个实施方案中，该方法包括IMS，C4和C4NP方法，焊料包括无铅焊料。 本发明还包括通过前述方法或方法生产的产品。

公开(公告)号：US20130001279A1

公开(公告)日：2013-01-03

申请号：US13613000

申请日：2012-09-13

Applicant: Kang-Wook Lee ,  Jae-Woong Nah ,  Nathalie Normand ,  Valerie Oberson

Inventor： Kang-Wook Lee ,  Jae-Woong Nah ,  Nathalie Normand ,  Valerie Oberson

IPC: B23K31/02

CPC classification number: B23K1/0016 ,  B23K35/3601 ,  B23K35/362

Abstract: The present invention is directed to a soldering method for joining objects is also provided, comprising the steps of applying a flux composition to at least a portion of one or more of the objects, and joining the objects.

Abstract translation: 本发明还涉及一种用于接合物体的焊接方法，其包括以下步骤：将焊剂组合物施加到一个或多个物体的至少一部分上并连接物体。

公开(公告)号：US08069685B2

公开(公告)日：2011-12-06

申请号：US12320071

申请日：2009-01-15

Applicant: Hyuk Nam ,  Kang-Wook Lee ,  Seung-Hyoung Ha ,  Geun-Hyoung Lee

Inventor： Hyuk Nam ,  Kang-Wook Lee ,  Seung-Hyoung Ha ,  Geun-Hyoung Lee

IPC: F25B49/00 ,  H02K21/12 ,  H02P23/00

CPC classification number: F25B49/025 ,  F25B2400/0751 ,  F25B2500/26 ,  F25B2600/021 ,  F25B2600/0251 ,  Y02B30/741

Abstract: Provided is an air conditioning system comprised of a plurality of indoor units connected to each other in parallel, each having an expansion valve, and an outdoor unit including a plurality of compressors, in which at least one of the compressors provided to the outdoor unit is a capacity modulation compressor including an electromotive driving unit for driving a plurality of compression units capable of selectively compressing a working fluid, and the electromotive driving unit for the capacity modulation compressor has a stator with a coil wound around thereon and a rotor rotating inside the stator, the rotor being an LSPRM including a rotor core, flux barriers, permanent magnets and conductive bars.

Abstract translation: 本发明提供一种空调系统，包括并联连接的多个室内机组，各室具有膨胀阀，以及包括多个压缩机的室外机组，其中设置于室外机组的至少一个压缩机为 一种容量调制压缩机，包括用于驱动能够选择性地压缩工作流体的多个压缩单元的电动驱动单元，并且用于容量调节压缩机的电动驱动单元具有卷绕在其上的线圈的定子和在定子内旋转的转子 转子是包括转子芯，磁通屏障，永磁体和导电棒的LSPRM。

公开(公告)号：US07938976B2

公开(公告)日：2011-05-10

申请号：US11679247

申请日：2007-02-27

Applicant: Kang-Wook Lee

Inventor： Kang-Wook Lee

IPC: C23F1/00 ,  H01L21/302

CPC classification number: H01L21/02082

Abstract: A method for removing undesirable contaminants from a chip passivation layer surface without creating SiO2 particles on the passivation layer, wherein the undesirable contaminants include graphitic layers and fluorinated layers. The use of N2 plasma with optimized plasma parameters can remove through etching both the graphitic and fluorinated organic layers. The best condition for the N2 plasma treatment is to use a relatively low-power within the range of 100-200 W and a relatively high vacuum pressure of N2 in the range of 500-750 mTorr.

Abstract translation: 一种用于从芯片钝化层表面去除不期望的污染物而不在钝化层上产生SiO 2颗粒的方法，其中不需要的污染物包括石墨层和氟化层。 使用具有优化等离子体参数的N2等离子体可以通过蚀刻石墨和氟化有机层来去除。 N2等离子体处理的最佳条件是在100-200W的范围内使用相对较低的功率，并且在500-750mTorr的范围内使用较高的N2的真空压力。

公开(公告)号：US07824959B2

公开(公告)日：2010-11-02

申请号：US11727760

申请日：2007-03-28

Applicant: Kang-Wook Lee ,  Se-Yong Oh ,  Young-Hee Song ,  Gu-Sung Kim

Inventor： Kang-Wook Lee ,  Se-Yong Oh ,  Young-Hee Song ,  Gu-Sung Kim

IPC: H01L21/44

CPC classification number: H01L25/50 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of forming a wafer level stack structure, including forming a first wafer including a first device chip, wherein the first device chip includes a plurality of input/output (I/O) pads, forming a second wafer including a second device chip, wherein each second device chip contains a second plurality of I/O pads, the second device chip is approximately equal in size to the first chip size, stacking the first wafer and the second wafer, and coupling the first wafer and the second wafer to each other. A method of forming a system-in-package for containing a wafer level stack structure, including forming a wafer level stack structure including a first device chip having a first plurality of input/output (I/O) pads and a second device chip having a second plurality of I/O pads, and forming a common circuit board to which the wafer level stack structure is connected.

Abstract translation: 一种形成晶片级堆叠结构的方法，包括形成包括第一器件芯片的第一晶片，其中所述第一器件芯片包括多个输入/输出（I / O）焊盘，形成包括第二器件芯片的第二晶片， 其中每个第二器件芯片包含第二多个I / O焊盘，所述第二器件芯片的大小与第一芯片尺寸大致相等，堆叠第一晶片和第二晶片，并将第一晶片和第二晶片耦合到每个 其他。 一种形成用于包含晶片级堆叠结构的系统级封装的方法，包括形成晶片级堆叠结构，其包括具有第一多个输入/输出（I / O）焊盘的第一器件芯片和具有第一器件芯片的第二器件芯片， 第二多个I / O焊盘，并且形成连接晶片级堆叠结构的公共电路板。

公开(公告)号：US07771541B2

公开(公告)日：2010-08-10

申请号：US11689570

申请日：2007-03-22

Applicant: Claude Blais ,  Eric Duchesne ,  Kang-Wook Lee ,  Sylvain Ouimet ,  Gerald J. Scilla

Inventor： Claude Blais ,  Eric Duchesne ,  Kang-Wook Lee ,  Sylvain Ouimet ,  Gerald J. Scilla

IPC: B08B7/00 ,  C23F1/00

CPC classification number: H01L21/02057 ,  H01L23/3128 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/0401

Abstract: A method of removing and/or reducing undesirable contaminants removes residues including graphitic layers, fluorinate layers, calcium sulfate (CaSO4) particles, tin oxides and organotin, from a chip passivation layer surface. The method uses a plasma process with an argon and oxygen mixture with optimized plasma parameters to remove both the graphitic and fluorinated layers and to reduce the level of the inorganic/tin oxides/organotin residue from an integrated circuit wafer while keeping the re-deposition of metallic compounds is negligible. This invention discloses the plasma processes that organics are not re-deposited from polymers to solder ball surfaces and tin oxide thickness does not increase on solder balls. The ratio of argon/oxygen is from about 50% to about 99% Ar and about 1% to about 50% O2 by volume. Incoming wafers, after treatment, are then diced to form individual chips that are employed to produce flip chip plastic ball grid array packages.

Abstract translation: 去除和/或减少不需要的污染物的方法从芯片钝化层表面去除残留物，包括石墨层，氟化物层，硫酸钙（CaSO 4）颗粒，氧化锡和有机锡。 该方法使用具有优化的等离子体参数的具有氩和氧混合物的等离子体处理以除去石墨和氟化层，并且从集成电路晶片中降低无机/锡氧化物/有机锡残余物的水平，同时保持重新沉积 金属化合物可忽略不计。 本发明公开了等离子体方法，有机物不会从聚合物重新沉积到焊球表面，氧化锡厚度在焊球上不增加。 氩/氧的比例为约50％至约99％Ar和约1％至约50％体积的O 2。 接下来的处理后的晶片被切割成用于制造倒装芯片塑料球栅阵列封装的单个芯片。