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    SELF-AWARE SEMICONDUCTOR EQUIPMENT
    51.
    发明申请
    SELF-AWARE SEMICONDUCTOR EQUIPMENT 审中-公开
    自主研发的半导体设备

    公开(公告)号：US20090112520A1

    公开(公告)日：2009-04-30

    申请号：US11929338

    申请日：2007-10-30

    Applicant: DIMITRIS LYMBEROPOULOS ,  Robin Cheung

    Inventor： DIMITRIS LYMBEROPOULOS ,  Robin Cheung

    IPC: G06F15/00

    CPC classification number: G06F11/24

    Abstract: The present invention provides methods and apparatus for predictive maintenance of semiconductor process equipment. In some embodiments, a method for performing predictive maintenance on semiconductor processing equipment includes performing at least one self-diagnostic test on the semiconductor processing equipment with no substrate present in the equipment; comparing a result of the at least one self diagnostic test to at least one baseline characterization of the equipment; and determining whether equipment maintenance is required based upon the comparison.

    Abstract translation: 本发明提供了用于半导体工艺设备的预测维护的方法和装置。 在一些实施例中，用于对半导体处理设备执行预测性维护的方法包括在半导体处理设备上执行至少一个自诊断测试，而不存在设备中的衬底; 将所述至少一个自诊断测试的结果与所述设备的至少一个基线表征进行比较; 并且基于比较来确定是否需要设备维护。

    Method and apparatus for providing intra-tool monitoring and control
    54.
    发明授权
    Method and apparatus for providing intra-tool monitoring and control 有权

    公开(公告)号：US07074626B2

    公开(公告)日：2006-07-11

    申请号：US10804324

    申请日：2004-03-19

    Applicant: Suketu Parikh ,  Robin Cheung

    Inventor： Suketu Parikh ,  Robin Cheung

    IPC: H01L21/00 ,  H01L21/66

    CPC classification number: H01L22/20 ,  G05B19/4187 ,  G05B19/41875 ,  G05B2219/32179 ,  G05B2219/32182 ,  G05B2219/45031 ,  Y02P90/14 ,  Y02P90/205 ,  Y02P90/22

    Abstract: A method and apparatus for performing intra-tool monitoring and control within a multi-step processing system. The method monitors the processing of a workpiece as the workpiece is processed by independently operating processing tools and produces control parameters for the various independently operating processing tools to optimize the processing of the workpiece. More specifically, the apparatus provides a metrology station located between each of a plurality of semiconductor wafer processing tools such that measurements can be made on wafers as they are passed from one tool to another providing intra tool monitoring. The data collected by the metrology station is coupled to a metrology data analyzer, which determines whether any of the plurality of wafer processing tools should be adjusted to improve the processing of the overall wafer. As such, the output of the metrology data analyzer provides control parameters to process controllers connected controllers connected to each of the tools within the semiconductor wafer processing system. Consequently, the operation of the metrology stations and the metrology data analyzer provides both feed forward and feed back data to control the tools based upon certain information that is gathered within the metrology station.

    Method of conditioning electrochemical baths in plating technology
    55.
    发明授权
    Method of conditioning electrochemical baths in plating technology 失效
    电镀技术中电化学浴的调理方法

    公开(公告)号：US06893548B2

    公开(公告)日：2005-05-17

    申请号：US09882208

    申请日：2001-06-13

    Applicant: Robin Cheung ,  Daniel A. Carl ,  Liang-Yuh Chen ,  Yezdi Dordi ,  Paul F. Smith ,  Ratson Morad ,  Peter Hey ,  Ashok Sinha

    Inventor： Robin Cheung ,  Daniel A. Carl ,  Liang-Yuh Chen ,  Yezdi Dordi ,  Paul F. Smith ,  Ratson Morad ,  Peter Hey ,  Ashok Sinha

    IPC: C23C18/16 ,  C25D7/12 ,  C25D21/12 ,  C25D21/18 ,  C25D5/00

    CPC classification number: C25D21/18 ,  C23C18/1617 ,  C23C18/1683 ,  C25D21/12

    Abstract: An apparatus and method is provided for analyzing or conditioning an electrochemical bath. One aspect of the invention provides a method for analyzing an electrochemical bath in an electrochemical deposition process including providing a first electrochemical bath having a first bath composition, utilizing the first electrochemical bath in an electrochemical deposition process to form a second electrochemical bath having a second bath composition and analyzing the first and second compositions to identify one or more constituents generated in the electrochemical deposition process. Additive material having a composition that is substantially the same as all or at least some of the one or more constituents generated in the electrochemical deposition process may be added to another electrochemical bath to produce a desired chemical composition. The constituents may be added at the beginning of the use of the bath to initially condition the electrochemical bath or may be added, preferably either continuously or periodically, during the electrochemical deposition process.

    Abstract translation: 提供了一种用于分析或调理电化学浴的装置和方法。 本发明的一个方面提供了一种用于在电化学沉积方法中分析电化学浴的方法，包括提供具有第一浴组成的第一电化学浴，利用电化学沉积工艺中的第一电化学浴形成具有第二浴的第二电化学浴 组合和分析第一和第二组合物以鉴定在电化学沉积过程中产生的一种或多种成分。 具有与在电化学沉积工艺中产生的一种或多种成分中的全部或至少一些基本上相同的组成的添加剂材料可以加入到另一电化学浴中以产生所需的化学组成。 可以在使用浴的开始时添加组分以最初调节电化学浴，或者可以在电化学沉积过程期间连续地或周期性地添加。

    Method of manufacturing a semiconductor device with a low permittivity dielectric layer and contamination due to exposure to water
    56.
    发明授权
    Method of manufacturing a semiconductor device with a low permittivity dielectric layer and contamination due to exposure to water 失效
    制造具有低介电常数介电层的半导体器件和由于暴露于水而引起的污染的方法

    公开(公告)号：US6117763A

    公开(公告)日：2000-09-12

    申请号：US939066

    申请日：1997-09-29

    Applicant: Charles May ,  Robin Cheung

    Inventor： Charles May ,  Robin Cheung

    IPC: H01L21/3105 ,  H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H01L23/532 ,  H01L21/4763

    CPC classification number: H01L23/5329 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/3121 ,  H01L21/31629 ,  H01L2924/0002 ,  Y10S438/906

    Abstract: A method of making a semiconductor device includes forming a low permittivity dielectric layer over one or more conductive lines of a semiconductor device. The dielectric layer is made using a silicon-containing material having a relatively low permittivity including, for example, silicon oxyfluoride (SiO.sub.y F.sub.x) and hydrogen silsesquioxane (HSQ). An optional oxide layer may be formed over the dielectric layer. At least a portion of the dielectric layer and/or the optional oxide layer is subsequently removed to form a planar dielectric layer having a contaminated surface layer. The contaminated surface layer is due to exposure to water and is removed by, for example, exposing the surface to an acid, such as hydrofluoric acid.

    Abstract translation: 制造半导体器件的方法包括在半导体器件的一个或多个导电线上形成低介电常数介电层。 电介质层使用包含例如氟氧化硅（SiO y F x）和氢倍半硅氧烷（HSQ））的具有较低介电常数的含硅材料制成。 可以在电介质层上形成任选的氧化物层。 随后去除介电层和/或任选的氧化物层的至少一部分以形成具有污染表面层的平面介电层。 受污染的表面层是由于暴露于水而被除去，例如通过使表面暴露于酸如氢氟酸。

    Bias plasma deposition for selective low dielectric insulation
    57.
    发明授权
    Bias plasma deposition for selective low dielectric insulation 失效
    偏压等离子体沉积用于选择性低介电绝缘

    公开(公告)号：US5990557A

    公开(公告)日：1999-11-23

    申请号：US964430

    申请日：1997-11-04

    Applicant: Steven Avanzino ,  Darrell M. Erb ,  Robin Cheung ,  Rich Klein ,  Pervaiz Sultan

    Inventor： Steven Avanzino ,  Darrell M. Erb ,  Robin Cheung ,  Rich Klein ,  Pervaiz Sultan

    IPC: H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/485

    CPC classification number: H01L21/02164 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31612 ,  H01L21/7682 ,  H01L21/76837 ,  H01L23/5222 ,  H01L2924/0002

    Abstract: A method of forming low dielectric insulation between those pairs of conductive lines, of a level of interconnection for integrated circuits, having a gap of about 0.5 microns or less by depositing a nonconformal source with a poor step function for the insulating material, such as silane (SiH.sub.4) as the silicon (Si) source for silicon dioxide (SiO.sub.2), so as to create, in the gap, a large void whose dielectric constant is slightly greater than 1. After the formation of the void in the 0.5 microns or less gaps, the deposited nonconformal material is etched either simultaneously or sequentially along with deposition to fill the remaining gaps with void free insulation. The surface of the deposited insulating material is planarized at the desired thickness. Alternatively, a thin conformal insulating layer is first deposited as a liner on the conductive lines. The resulting structure of the interconnection level comprises a layer of insulation between and on the conductive lines with the dielectric constant of the insulation between the pairs of conductive lines with gap of 0.5 or less being, in combination with the void, at least about 3 or lower, and all of the remaining gaps are filled with void free insulating material with a dielectric constant of greater than about 3.5.

    Abstract translation: 在这些导电线对之间形成低介电绝缘的方法，该集成电路的互连级别通过沉积具有差的绝缘材料的步进功能的非共形源（例如硅烷）而具有约0.5微米或更小的间隙 （SiH4）作为二氧化硅（SiO 2）的硅（Si）源，以在间隙中产生介电常数略大于1的大空隙。在0.5微米或更小的空隙形成之后 间隙，沉积的非共形材料与沉积同时或顺序蚀刻，以用无空隙绝缘填充剩余的间隙。 沉积的绝缘材料的表面被平坦化为所需的厚度。 或者，首先在导电线上沉积薄的共形绝缘层作为衬垫。 所形成的互连级别的结构包括在导电线之间和之间的导电层之间的绝缘层，其中间隔为0.5或更小的导电线对之间的绝缘体的介电常数与空隙结合为至少约3或 较低，并且所有剩余的间隙都填充有绝缘材料，介电常数大于约3.5。

    Composite insulation with a dielectric constant of less than 3 in a narrow space separating conductive lines
    59.
    发明授权
    Composite insulation with a dielectric constant of less than 3 in a narrow space separating conductive lines 失效
    在狭窄的空间分离导线的介电常数小于3的复合绝缘

    公开(公告)号：US5691573A

    公开(公告)日：1997-11-25

    申请号：US481030

    申请日：1995-06-07

    Applicant: Steven Avanzino ,  Darrell M. Erb ,  Robin Cheung ,  Rich Klein

    Inventor： Steven Avanzino ,  Darrell M. Erb ,  Robin Cheung ,  Rich Klein

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/485 ,  H01L23/52

    CPC classification number: H01L23/5222 ,  H01L21/7682 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002

    Abstract: A method of forming low dielectric insulation between those pairs of conductive lines, of a level of interconnection for integrated circuits, having a gap of about 0.5 microns or less by depositing a nonconformal source with a poor step function for the insulating material, such as silane (SiH.sub.4) as the silicon (Si) source for silicon dioxide (SiO.sub.2), so as to create, in the gap, a large void whose dielectric constant is slightly greater than 1. After all of the conductive lines have received a deposit of conformal insulating material and a flowable insulating material, the composite insulating materials are removed, preferably by etching, from those pairs of conductive lines with a gap of about 0.5 microns or less. Now, a nonconformal insulating material with a poor step function is deposited and creates a large void in the open gaps of 0.5 microns or less. After creating the void, the deposition continues and is planarized at the desired composite thickness of insulation. Alternatively, a thin conformal insulating layer is first deposited as a liner on the conductive lines. The resulting structure of the interconnection level comprises a layer of insulation between and on the conductive lines with the dielectric constant of the insulation between the pairs of conductive lines with the gap of 0.5 or less being, in combination with the void, at least about 3 or lower, and all of the remaining gaps are filled with the flowable insulating material and are void free with a composite dielectric constant of greater than about 3.5.

    Abstract translation: 在这些导电线对之间形成低介电绝缘的方法，该集成电路的互连级别具有约0.5微米或更小的间隙，通过沉积具有差的绝缘材料的步进功能的非共形源，例如硅烷 （SiH4）作为二氧化硅（SiO 2）的硅（Si）源，以在间隙中产生介电常数略大于1的大空隙。在所有导电线都已经接收到保形膜 绝缘材料和可流动的绝缘材料，优选通过蚀刻从具有约0.5微米或更小的间隙的那对导电线去除复合绝缘材料。 现在，沉积具有差的阶梯函数的非共形绝缘材料，并且在0.5微米或更小的开放间隙中产生大的空隙。 在形成空隙之后，沉积继续并且在所需的绝缘复合厚度下被平坦化。 或者，首先在导电线上沉积薄的共形绝缘层作为衬垫。 所得到的互连级别的结构包括在导电线之间和之间的导电层之间的绝缘层，导电线对之间的绝缘介电常数为0.5或更小的间隙，与空隙结合为至少约3 或更低，并且所有剩余间隙都填充有可流动绝缘材料，并且无复合介电常数大于约3.5。

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