Abstract:
A circuit substrate has the following elements. A stacked circuit structure has a first surface and a second surface opposite thereto surface. A first patterned inner conductive layer is disposed on the first surface and has multiple pads. A first patterned outer conductive layer is disposed on the patterned inner conductive layer and has multiple conductive pillars, wherein each of the first conductive pillar is located on the corresponding first pad. The first dielectric layer covers the first surface, the first patterned inner conductive layer and the first patterned outer conductive layer, and has multiple first concaves, wherein the first concave exposes the top and side of the corresponding first conductive pillar. A semiconductor package structure applied the above circuit substrate and a process for fabricating the same are also provided here.
Abstract:
A method for aligning signals on a bus, including: replicating propagation path lengths, loads, and buffering of a radial distribution network for a strobe; receiving a first signal, and generating a second signal by employing the replicated propagation path lengths, loads, and buffering; receiving control information over a standard JTAG bus, wherein the control information indicates an amount to adjust a propagation time; and measuring the propagation time beginning with assertion of the first signal and ending with assertion of the second signal, said measuring comprising: selecting one of a plurality of successively delayed versions of the first signal that coincides with assertion of the second signal; adjusting the propagation time by the amount prescribed by the control information to yield an adjusted propagation time; and gray encoding the adjusted propagation time to generate a value on a lag bus.
Abstract:
A circuit substrate has the following elements. A stacked circuit structure has a first surface and a second surface opposite thereto surface. A first patterned inner conductive layer is disposed on the first surface and has multiple pads. A first patterned outer conductive layer is disposed on the patterned inner conductive layer and has multiple conductive pillars, wherein each of the first conductive pillar is located on the corresponding first pad. The first dielectric layer covers the first surface, the first patterned inner conductive layer and the first patterned outer conductive layer, and has multiple first concaves, wherein the first concave exposes the top and side of the corresponding first conductive pillar. A semiconductor package structure applied the above circuit substrate and a process for fabricating the same are also provided here.
Abstract:
A natural language dialog system and a method capable of correcting a speech response are provided. The method includes following steps. A first speech input is received. At least one keyword included in the first speech input is parsed to obtain a candidate list having at least one report answers. One of the report answers is selected from the candidate list as a first report answer, and a first speech response is output according to the first report answer. A second speech input is received and parsed to determine whether the first report answer is correct. If the first report answer is incorrect, another report answer other than the first report answer is selected from the candidate list as a second report answer. According to the second report answer, a second speech response is output.
Abstract:
An integrated circuit including a global supply bus, a gated supply bus, a functional circuit coupled to the gated supply bus, a programmable device that stores a programmed control parameter, and a digital power gating system. The digital power gating system includes gating devices and a power gating control system. Each gating device is coupled between the global and gated supply buses and each has a control terminal. The power gating control system controls a digital control value to control activation of the gating devices. The power gating control system is configured to perform a power gating operation by adjusting the digital control value to control a voltage of the gated supply bus relative to the voltage of the global supply bus. The power gating operation may be adjusted using the programmed control parameter. The programmable device may be a fuse array or a memory programmed with programmed control parameter.
Abstract:
A pin arrangement adapted to a FPC connector is provided. The pin arrangement includes a pin lane. The pin lane includes a pair of ground pins, a pair of differential pins and at least one not-connected (NC) pin. The differential pins are located between the pair of ground pins. The at least one NC pin is located between the pair of differential pins or between one of the pair of ground pins and one of the pair of differential pins adjacent thereto. By adding the at least one NC pin between the pair of differential pins and/or between the differential pin and the ground pin adjacent thereto, a distance between each of the pair of the differential pins and/or between the differential pin and the ground pin is increased, and thus a differential characteristic impedance of the pair of differential pins is raised to reduce the impact of impedance mismatch.
Abstract:
A method for dynamically reconfiguring one or more cores of a multi-core microprocessor comprising a plurality of cores and sideband communication wires, extrinsic to a system bus connected to a chipset, which facilitate non-system-bus inter-core communications. At least some of the cores are operable to be reconfigurably designated with or without master credentials for purposes of structuring sideband-based inter-core communications. The method includes determining an initial configuration of cores of the microprocessor, which configuration designates at least one core, but not all of the cores, as a master core, and reconfiguring the cores according to a modified configuration, which modified configuration removes a master designation from a core initially so designated, and assigns a master designation to a core not initially so designated. Each core is configured to conditionally drive a sideband communication wire to which it is connected based upon its designation, or lack thereof, as a master core.
Abstract:
A multi-core microprocessor supports a plurality of operating states that provide different levels of performance and power consumption to the microprocessor and its cores. A control unit puts selected cores into selected operating states at selected times. A core-specific synchronization register is provided for each core external to the core and readable by the control unit. Each core responds to an instruction to target an operating state by writing a value identifying the target operating state to the synchronization register. The control unit causes power saving actions that affect shared resources provided that the actions do not reduce performance of any core sharing the resources below the core's target operating state.
Abstract:
The invention provides a memory device. The memory device includes a flash memory, a memory, and a controller. The flash memory includes a plurality of blocks for data storage. The memory stores an address mapping table recording relationships between logical addresses and physical addresses of the blocks therein. The controller divides the address mapping table stored in the memory to a plurality of mapping table units, updates relationships between the logical addresses and the physical addresses stored in the mapping table units, determines whether data access performed to the flash memory fulfills the conditions of a specific requirement, and when the data access fulfills the conditions of the specific requirement, the controller selects a target mapping table unit from the mapping table units, and stores the target mapping table unit and a corresponding time stamp as a mapping table unit data to the flash memory.
Abstract:
A microprocessor includes hardware registers that instantiate the Intel 64 Architecture R8-R15 GPRs. The microprocessor associates with each of the R8-R15 GPRs a respective unique MSR address. The microprocessor also includes hardware registers that instantiate the ARM Architecture GPRs. In response to an ARM MRRC instruction that specifies the respective unique MSR address of one of the R8-R15 GPRs, the microprocessor reads the contents of the hardware register that instantiates the specified one of the R8-R15 GPRs into the hardware registers that instantiate two of the ARM GPRs registers. In response to an ARM MCRR instruction that specifies the respective unique MSR address of one of the R8-R15 GPRs, the microprocessor writes into the hardware register that instantiates the specified one of the R8-R15 GPRs the contents of the hardware registers that instantiate two of the ARM Architecture GPRs registers. The hardware registers may be shared by the two Architectures.