公开(公告)号：US20170025343A1

公开(公告)日：2017-01-26

申请号：US15284514

申请日：2016-10-03

Applicant: VIA Technologies, Inc.

Inventor： Chen-Yueh Kung

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/367 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4882 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3185 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/10 ,  H01L2224/16157 ,  H01L2224/73204 ,  H05K1/112 ,  H05K1/119 ,  H05K1/181 ,  H05K3/0026 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/09472 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2203/0723 ,  H05K2203/107 ,  H05K2203/1476 ,  Y10T29/49156

Abstract: A circuit substrate has the following elements. A stacked circuit structure has a first surface and a second surface opposite thereto surface. A first patterned inner conductive layer is disposed on the first surface and has multiple pads. A first patterned outer conductive layer is disposed on the patterned inner conductive layer and has multiple conductive pillars, wherein each of the first conductive pillar is located on the corresponding first pad. The first dielectric layer covers the first surface, the first patterned inner conductive layer and the first patterned outer conductive layer, and has multiple first concaves, wherein the first concave exposes the top and side of the corresponding first conductive pillar. A semiconductor package structure applied the above circuit substrate and a process for fabricating the same are also provided here.

Abstract translation: 电路基板具有以下元件。 层叠电路结构具有与其相对的第一表面和第二表面。 第一图案化内导电层设置在第一表面上并具有多个焊盘。 第一图案化外导电层设置在图案化的内导电层上并且具有多个导电柱，其中第一导电柱中的每一个位于相应的第一焊盘上。 第一介电层覆盖第一表面，第一图案化内导电层和第一图案化外导电层，并且具有多个第一凹部，其中第一凹部暴露对应的第一导电柱的顶部和侧面。 应用上述电路基板的半导体封装结构及其制造方法也在这里提供。

公开(公告)号：US09552321B2

公开(公告)日：2017-01-24

申请号：US13757480

申请日：2013-02-01

Applicant: VIA Technologies, Inc.

Inventor： Vanessa S. Canac ,  James R. Lundberg

IPC: G06F13/42

CPC classification number: G06F13/4243 ,  G06F1/12 ,  G06F13/4217 ,  G11C7/1072 ,  G11C8/18

Abstract: A method for aligning signals on a bus, including: replicating propagation path lengths, loads, and buffering of a radial distribution network for a strobe; receiving a first signal, and generating a second signal by employing the replicated propagation path lengths, loads, and buffering; receiving control information over a standard JTAG bus, wherein the control information indicates an amount to adjust a propagation time; and measuring the propagation time beginning with assertion of the first signal and ending with assertion of the second signal, said measuring comprising: selecting one of a plurality of successively delayed versions of the first signal that coincides with assertion of the second signal; adjusting the propagation time by the amount prescribed by the control information to yield an adjusted propagation time; and gray encoding the adjusted propagation time to generate a value on a lag bus.

Abstract translation: 一种用于在总线上对准信号的方法，包括：复制用于选通的径向分布网络的传播路径长度，负载和缓冲; 接收第一信号，并通过采用复制的传播路径长度，加载和缓冲来产生第二信号; 通过标准JTAG总线接收控制信息，其中所述控制信息指示调整传播时间的量; 并且测量从所述第一信号的断言开始并以所述第二信号的断言结束的所述传播时间，所述测量包括：选择与所述第二信号的断言一致的所述第一信号的多个连续延迟版本中的一个; 将传播时间调整为由控制信息规定的量，以产生经调整的传播时间; 并且对经调整的传播时间灰度编码以在滞后总线上产生一个值。

公开(公告)号：US09497864B2

公开(公告)日：2016-11-15

申请号：US13898486

申请日：2013-05-21

Applicant: VIA Technologies, Inc.

Inventor： Chen-Yueh Kung

IPC: H05K1/18 ,  H05K1/11 ,  H05K3/40 ,  H05K3/00 ,  H01L23/13 ,  H01L23/367 ,  H01L23/498 ,  H05K3/28

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4882 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3185 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/10 ,  H01L2224/16157 ,  H01L2224/73204 ,  H05K1/112 ,  H05K1/119 ,  H05K1/181 ,  H05K3/0026 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/09472 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2203/0723 ,  H05K2203/107 ,  H05K2203/1476 ,  Y10T29/49156

Abstract: A circuit substrate has the following elements. A stacked circuit structure has a first surface and a second surface opposite thereto surface. A first patterned inner conductive layer is disposed on the first surface and has multiple pads. A first patterned outer conductive layer is disposed on the patterned inner conductive layer and has multiple conductive pillars, wherein each of the first conductive pillar is located on the corresponding first pad. The first dielectric layer covers the first surface, the first patterned inner conductive layer and the first patterned outer conductive layer, and has multiple first concaves, wherein the first concave exposes the top and side of the corresponding first conductive pillar. A semiconductor package structure applied the above circuit substrate and a process for fabricating the same are also provided here.

Abstract translation: 电路基板具有以下元件。 层叠电路结构具有与其相对的第一表面和第二表面。 第一图案化内导电层设置在第一表面上并具有多个焊盘。 第一图案化外导电层设置在图案化的内导电层上并且具有多个导电柱，其中第一导电柱中的每一个位于相应的第一焊盘上。 第一介电层覆盖第一表面，第一图案化内导电层和第一图案化外导电层，并且具有多个第一凹部，其中第一凹部暴露对应的第一导电柱的顶部和侧面。 应用上述电路基板的半导体封装结构及其制造方法也在这里提供。

公开(公告)号：US09466295B2

公开(公告)日：2016-10-11

申请号：US14142932

申请日：2013-12-30

Applicant: VIA Technologies, Inc.

Inventor： Guo-Feng Zhang

IPC: G10L15/22 ,  G10L15/08 ,  G10L15/18

CPC classification number: G10L15/22 ,  G10L15/1822 ,  G10L2015/088

Abstract: A natural language dialog system and a method capable of correcting a speech response are provided. The method includes following steps. A first speech input is received. At least one keyword included in the first speech input is parsed to obtain a candidate list having at least one report answers. One of the report answers is selected from the candidate list as a first report answer, and a first speech response is output according to the first report answer. A second speech input is received and parsed to determine whether the first report answer is correct. If the first report answer is incorrect, another report answer other than the first report answer is selected from the candidate list as a second report answer. According to the second report answer, a second speech response is output.

Abstract translation: 提供了一种自然语言对话系统和能够校正语音响应的方法。 该方法包括以下步骤。 接收到第一个语音输入。 解析包含在第一语音输入中的至少一个关键字以获得具有至少一个报告答案的候选列表。 从候选列表中选择报告答案之一作为第一报告答案，并且根据第一报告答案输出第一语音响应。 接收并解析第二个语音输入，以确定第一个报告答案是否正确。 如果第一个报告答案不正确，则从候选人名单中选出除第一个报告答复之外的其他报告回答作为第二个报告答案。 根据第二报告答案，输出第二个语音响应。

公开(公告)号：US09450580B2

公开(公告)日：2016-09-20

申请号：US14202313

申请日：2014-03-10

Applicant: VIA TECHNOLOGIES, INC.

Inventor： James R. Lundberg

IPC: G05F1/10 ,  H03K19/00

CPC classification number: H03K19/0008

Abstract: An integrated circuit including a global supply bus, a gated supply bus, a functional circuit coupled to the gated supply bus, a programmable device that stores a programmed control parameter, and a digital power gating system. The digital power gating system includes gating devices and a power gating control system. Each gating device is coupled between the global and gated supply buses and each has a control terminal. The power gating control system controls a digital control value to control activation of the gating devices. The power gating control system is configured to perform a power gating operation by adjusting the digital control value to control a voltage of the gated supply bus relative to the voltage of the global supply bus. The power gating operation may be adjusted using the programmed control parameter. The programmable device may be a fuse array or a memory programmed with programmed control parameter.

Abstract translation: 包括全局电源总线，门控电源总线，耦合到门控电源总线的功能电路，存储编程控制参数的可编程器件和数字电源门控系统的集成电路。 数字电源门控系统包括门控设备和电源门控控制系统。 每个选通装置耦合在全局和门控供电总线之间，并且每个具有控制终端。 电源门控控制系统控制数字控制值以控制门控设备的激活。 电源门控控制系统被配置为通过调整数字控制值来执行电力门控操作，以控制门控电源总线相对于全局电源总线的电压的电压。 电源门控操作可以使用编程的控制参数进行调整。 可编程器件可以是保险丝阵列或用编程控制参数编程的存储器。

公开(公告)号：US09444165B2

公开(公告)日：2016-09-13

申请号：US14551094

申请日：2014-11-24

Applicant: VIA Technologies, Inc.

Inventor： Sheng-Yuan Lee

IPC: H01R12/00 ,  H01R12/77 ,  H05K1/02 ,  H05K1/14 ,  H01R13/6473 ,  H01R13/6471 ,  H05K1/11

CPC classification number: H01R12/771 ,  H01R13/6471 ,  H01R13/6473 ,  H05K1/025 ,  H05K1/117 ,  H05K1/118 ,  H05K1/147 ,  H05K2201/09781 ,  H05K2201/10189

Abstract: A pin arrangement adapted to a FPC connector is provided. The pin arrangement includes a pin lane. The pin lane includes a pair of ground pins, a pair of differential pins and at least one not-connected (NC) pin. The differential pins are located between the pair of ground pins. The at least one NC pin is located between the pair of differential pins or between one of the pair of ground pins and one of the pair of differential pins adjacent thereto. By adding the at least one NC pin between the pair of differential pins and/or between the differential pin and the ground pin adjacent thereto, a distance between each of the pair of the differential pins and/or between the differential pin and the ground pin is increased, and thus a differential characteristic impedance of the pair of differential pins is raised to reduce the impact of impedance mismatch.

Abstract translation: 提供一种适于FPC连接器的插脚布置。 引脚布置包括引脚通道。 引脚通道包括一对接地引脚，一对差分引脚和至少一个未连接（NC）引脚。 差分引脚位于一对接地引脚之间。 所述至少一个NC销位于所述一对差动销之间，或位于所述一对接地引脚中的一个与所述一对接地引脚中的一个与其相邻的所述一对差动引脚之一中。 通过在所述一对差动引脚之间和/或差分引脚和与其相邻的接地引脚之间增加至少一个NC引脚，所述一对差动引脚和/或差分引脚与接地引脚之间的距离 因此增加了一对差分引脚的差分特性阻抗，以减少阻抗失配的影响。

公开(公告)号：US09367497B2

公开(公告)日：2016-06-14

申请号：US14522931

申请日：2014-10-24

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Stephan Gaskins

IPC: G06F13/36 ,  G06F15/163 ,  G06F1/32 ,  G06F1/24 ,  G06F9/30 ,  G06F9/50 ,  G06F9/445 ,  G06F15/82 ,  G06F11/36 ,  G06F11/14

CPC classification number: G06F1/26 ,  G06F1/24 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/30076 ,  G06F9/30083 ,  G06F9/44505 ,  G06F9/5094 ,  G06F11/1423 ,  G06F11/3664 ,  G06F13/36 ,  G06F15/163 ,  G06F15/82 ,  Y02D10/14 ,  Y02D10/22

Abstract: A method for dynamically reconfiguring one or more cores of a multi-core microprocessor comprising a plurality of cores and sideband communication wires, extrinsic to a system bus connected to a chipset, which facilitate non-system-bus inter-core communications. At least some of the cores are operable to be reconfigurably designated with or without master credentials for purposes of structuring sideband-based inter-core communications. The method includes determining an initial configuration of cores of the microprocessor, which configuration designates at least one core, but not all of the cores, as a master core, and reconfiguring the cores according to a modified configuration, which modified configuration removes a master designation from a core initially so designated, and assigns a master designation to a core not initially so designated. Each core is configured to conditionally drive a sideband communication wire to which it is connected based upon its designation, or lack thereof, as a master core.

Abstract translation: 一种用于动态重新配置多核微处理器的一个或多个核心的方法，所述多核微处理器包括多个核心和边带通信线路，其外部连接到连接到芯片组的系统总线，这有助于非系统总线核心间通信。 为了构建基于边带的核心间通信的目的，至少一些核可操作以可重新配置地指定或不具有主凭证。 该方法包括确定微处理器的核心的初始配置，该配置指定至少一个核心，但不将所有核心指定为主核心，并且根据修改的配置重新配置核心，该修改的配置删除主命名 从最初如此指定的核心，并将主指定分配给最初未指定的核心。 每个核心被配置为基于其指定或不存在作为主核心有条件地驱动其所连接的边带通信线。

公开(公告)号：US20160162017A1

公开(公告)日：2016-06-09

申请号：US14994544

申请日：2016-01-13

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. GLENN HENRY ,  TERRY PARKS

IPC: G06F1/32 ,  G06F12/08

CPC classification number: G06F1/3287 ,  G06F1/04 ,  G06F1/32 ,  G06F9/522 ,  G06F12/0891 ,  G06F2212/1028 ,  G06F2212/60

Abstract: A multi-core microprocessor supports a plurality of operating states that provide different levels of performance and power consumption to the microprocessor and its cores. A control unit puts selected cores into selected operating states at selected times. A core-specific synchronization register is provided for each core external to the core and readable by the control unit. Each core responds to an instruction to target an operating state by writing a value identifying the target operating state to the synchronization register. The control unit causes power saving actions that affect shared resources provided that the actions do not reduce performance of any core sharing the resources below the core's target operating state.

Abstract translation: 多核微处理器支持向微处理器及其核心提供不同级别的性能和功耗的多个操作状态。 控制单元在所选择的时间将选定的磁芯置于选定的运行状态。 为核心外部的每个核心提供核心特定同步寄存器，并由控制单元读取。 每个核心通过将标识目标操作状态的值写入同步寄存器来响应指令以对准操作状态的指令。 如果行为不降低任何核心共享低于核心目标操作状态的资源的核心，控制单元就会产生影响共享资源的省电动作。

公开(公告)号：US09329995B2

公开(公告)日：2016-05-03

申请号：US14548549

申请日：2014-11-20

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Liang Chen ,  Chen Xiu

IPC: G06F12/02 ,  G06F11/14

CPC classification number: G06F12/0246 ,  G06F11/1441 ,  G06F2212/7201 ,  Y02D10/13

Abstract: The invention provides a memory device. The memory device includes a flash memory, a memory, and a controller. The flash memory includes a plurality of blocks for data storage. The memory stores an address mapping table recording relationships between logical addresses and physical addresses of the blocks therein. The controller divides the address mapping table stored in the memory to a plurality of mapping table units, updates relationships between the logical addresses and the physical addresses stored in the mapping table units, determines whether data access performed to the flash memory fulfills the conditions of a specific requirement, and when the data access fulfills the conditions of the specific requirement, the controller selects a target mapping table unit from the mapping table units, and stores the target mapping table unit and a corresponding time stamp as a mapping table unit data to the flash memory.

Abstract translation: 本发明提供一种存储装置。 存储器件包括闪存，存储器和控制器。 闪存包括用于数据存储的多个块。 存储器存储记录其中的块的逻辑地址和物理地址之间的关系的地址映射表。 控制器将存储在存储器中的地址映射表分成多个映射表单元，更新存储在映射表单元中的逻辑地址和物理地址之间的关系，确定对闪速存储器执行的数据访问是否满足条件 特定要求，并且当数据访问满足特定要求的条件时，控制器从映射表单元中选择目标映射表单元，并将目标映射表单元和对应的时间戳作为映射表单元数据存储到 闪存

公开(公告)号：US09292470B2

公开(公告)日：2016-03-22

申请号：US13874878

申请日：2013-05-01

Applicant: VIA Technologies, Inc.

Inventor： Mark John Ebersole

IPC: G06F9/22 ,  G06F15/78 ,  G06F9/30 ,  G06F9/44

CPC classification number: G06F15/7842 ,  G06F9/30076 ,  G06F9/30112 ,  G06F9/30138 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/4401

Abstract: A microprocessor includes hardware registers that instantiate the Intel 64 Architecture R8-R15 GPRs. The microprocessor associates with each of the R8-R15 GPRs a respective unique MSR address. The microprocessor also includes hardware registers that instantiate the ARM Architecture GPRs. In response to an ARM MRRC instruction that specifies the respective unique MSR address of one of the R8-R15 GPRs, the microprocessor reads the contents of the hardware register that instantiates the specified one of the R8-R15 GPRs into the hardware registers that instantiate two of the ARM GPRs registers. In response to an ARM MCRR instruction that specifies the respective unique MSR address of one of the R8-R15 GPRs, the microprocessor writes into the hardware register that instantiates the specified one of the R8-R15 GPRs the contents of the hardware registers that instantiate two of the ARM Architecture GPRs registers. The hardware registers may be shared by the two Architectures.

Abstract translation: 微处理器包括实例化Intel 64架构R8-R15 GPR的硬件寄存器。 微处理器与每个R8-R15 GPR相关联，分别有独特的MSR地址。 微处理器还包括实例化ARM架构GPR的硬件寄存器。 为了响应指定R8-R15 GPR之一的相应唯一MSR地址的ARM MRRC指令，微处理器读取硬件寄存器中将指定的一个R8-R15 GPR实例化为硬件寄存器的内容，该硬件寄存器实例化为二 的ARM GPR寄存器。 为了响应指定R8-R15 GPR之一的相应唯一MSR地址的ARM MCRR指令，微处理器写入硬件寄存器，将R8-R15 GPR中指定的一个实例化为硬件寄存器的内容，实例化了两个 的ARM架构GPR寄存器。 硬件寄存器可能由两个架构共享。