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86 条记录 (耗时 0.041 秒)

    Semiconductor memory
    55.
    发明申请
    Semiconductor memory 有权
    半导体存储器

    公开(公告)号：US20050190625A1

    公开(公告)日：2005-09-01

    申请号：US11098557

    申请日：2005-04-05

    申请人： Yasurou Matsuzaki

    发明人： Yasurou Matsuzaki

    IPC分类号： G11C7/10 ,  G11C11/406 ,  G11C11/4063 ,  G11C7/00

    CPC分类号： G11C7/1045 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622 ,  G11C2211/4067

    摘要： Flags are formed to respectively correspond to memory cell groups each including volatile memory cells. Each flag indicates as a set state that the memory cells store data in a second memory mode. In a changing operation of changing from a first memory mode in which data is independently retained by each memory cell to a second memory mode in which same data are retained in the memory cells of each memory cell group, each flag is reset in response to the first access to the corresponding memory cell group. Therefore, only the first access is made in the second memory mode in each memory cell group. The memory cells are accessed in a mode according to the flag in the changing operation, thereby allowing a system managing the semiconductor memory to freely access the memory cells even during the changing operation. Consequently, a practical changing time can be eliminated.

    摘要翻译： 标志分别形成为分别对应于包括易失性存储单元的存储单元组。 每个标志指示存储器单元将数据存储在第二存储器模式中的设置状态。 在从每个存储器单元独立地保持数据的第一存储器模式改变为在每个存储单元组的存储单元中保留相同数据的第二存储器模式的改变操作中，每个标志响应于 首先访问相应的存储单元组。 因此，在每个存储单元组中仅在第二存储器模式中进行第一次访问。 存储单元按照改变操作中的标志在模式下访问，从而即使在改变操作期间也允许管理半导体存储器的系统自由地访问存储单元。 因此，可以消除实际的改变时间。

    Self-test circuit and memory device incorporating it
    56.
    发明授权
    Self-test circuit and memory device incorporating it 有权
    自检电路和结合其的存储器件

    公开(公告)号：US06907555B1

    公开(公告)日：2005-06-14

    申请号：US09691115

    申请日：2000-10-19

    申请人： Yukihiro Nomura ,  Hiroyuki Fujimoto ,  Takahiro Suzuki ,  Tatsuya Kanda ,  Yasurou Matsuzaki ,  Masahiko Saitou ,  Hiroyoshi Tomita

    发明人： Yukihiro Nomura ,  Hiroyuki Fujimoto ,  Takahiro Suzuki ,  Tatsuya Kanda ,  Yasurou Matsuzaki ,  Masahiko Saitou ,  Hiroyoshi Tomita

    IPC分类号： G01R31/28 ,  G01R31/3185 ,  G06F12/16 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/06 ,  G11C29/12 ,  G11C29/44

    CPC分类号： G11C29/44

    摘要： The present invention is a self-test circuit (BIST) incorporated in the memory device, which is activated in response to a test activation signal from outside. When this self-test circuit is activated in response to a test activation signal (WBIZ) from outside, it generates a test operation command (WBI-CMD), generates a test address (WBI-ADD), and generates test data (WBI-DATA). Furthermore, after the self-test circuit writes the test data to a memory cell, it effects a comparison to establish whether or not the read data that is read from this memory cell is the same as the test data that was written thereto and stores information as to the result of this comparison. This comparison result information is then output to the outside.

    摘要翻译： 本发明是一种结合在存储器件中的自检电路（BIST），其响应于来自外部的测试激活信号被激活。 当该自检电路响应于来自外部的测试激活信号（WBIZ）被激活时，它产生测试操作命令（WBI-CMD），生成测试地址（WBI-ADD），并生成测试数据（WBI- 数据）。 此外，在自检电路将测试数据写入存储单元之后，进行比较以确定从该存储单元读取的读取数据是否与写入的测试数据相同并存储信息 关于这个比较的结果。 然后将该比较结果信息输出到外部。

    Semiconductor memory
    57.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US06829192B2

    公开(公告)日：2004-12-07

    申请号：US10335949

    申请日：2003-01-03

    申请人： Naoharu Shinozaki ,  Yasurou Matsuzaki

    发明人： Naoharu Shinozaki ,  Yasurou Matsuzaki

    IPC分类号： G11C700

    CPC分类号： G11C11/40607 ,  G11C7/08 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091 ,  G11C2207/2227 ,  G11C2211/4067 ,  G11C2211/4068

    摘要： A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during the low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the first memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption during the low power consumption mode.

    摘要翻译： 在低功耗模式期间用于保留数据的部分区域由连接到位线的多个存储单元中的单个第一存储单元组成。 操作控制电路在正常操作模式期间操作根据地址信号选择的任何存储单元，以执行读操作和写操作。 操作控制电路在低功耗模式期间将由部分区域中的第一存储单元保留的数据保持为读出放大器。 这消除了在低功耗模式期间需要用于将数据保持在第一存储单元中的刷新操作。 由于可以在不进行刷新操作的情况下保持数据，因此可以在低功耗模式下降低功耗。

    DLL circuit adjustable with external load
    59.
    发明授权
    DLL circuit adjustable with external load 有权
    DLL电路可通过外部负载进行调节

    公开(公告)号：US06476653B1

    公开(公告)日：2002-11-05

    申请号：US09774172

    申请日：2001-02-01

    申请人： Yasurou Matsuzaki

    发明人： Yasurou Matsuzaki

    IPC分类号： H03L706

    CPC分类号： H03L7/0814

    摘要： The present invention provides a DLL circuit performing a phase adjustment in accordance to an output load, and capable of adjusting the phase in a shot time. In the present invention, in a delayed lock loop (DLL) circuit that generates a control clock having a prescribed phase relationship with a reference clock by delaying the reference clock, the operating delay time of an output buffer is measured and the timing of the control clock is adjusted in accordance with this operating delay time. As a result, the timing of the output clock of the first variable delay circuit delay circuit is adjusted in accordance with the magnitude of the external load. This output clock or the output clock of a separate variable delay circuit subject to the same delay control is then utilized as a control clock.

    摘要翻译： 本发明提供一种根据输出负载执行相位调整并且能够在拍摄时间内调节相位的DLL电路。 在本发明中，在延迟锁定环（DLL）电路中，通过延迟参考时钟产生与参考时钟具有规定相位关系的控制时钟，测量输出缓冲器的操作延迟时间，并且控制定时 时钟根据该操作延迟时间进行调整。 结果，根据外部负载的大小来调整第一可变延迟电路延迟电路的输出时钟的定时。 然后将该输出时钟或受到相同延迟控制的单独可变延迟电路的输出时钟用作控制时钟。

    Semiconductor memory device capable of reducing power consumption in self-refresh operation
    60.
    发明授权
    Semiconductor memory device capable of reducing power consumption in self-refresh operation 有权
    能够降低自刷新操作中的功耗的半导体存储器件

    公开(公告)号：US06349068B2

    公开(公告)日：2002-02-19

    申请号：US09828847

    申请日：2001-04-10

    申请人： Yoshihiro Takemae ,  Yasurou Matsuzaki

    发明人： Yoshihiro Takemae ,  Yasurou Matsuzaki

    IPC分类号： G11C700

    CPC分类号： G11C11/40622 ,  G11C11/406

    摘要： A semiconductor memory device, which refreshes memory cells to retain data, has a first refresh mode and a second refresh mode. The first refresh mode is a mode for refreshing all of the memory cells, and the second refresh mode is a mode for refreshing a part of the memory cells. By refreshing only designated areas where data must be retained, power consumption in a refresh operation can be reduced, drastically cutting power consumption in a power-down mode.

    摘要翻译： 刷新存储单元以保留数据的半导体存储器件具有第一刷新模式和第二刷新模式。 第一刷新模式是用于刷新所有存储单元的模式，第二刷新模式是用于刷新存储单元的一部分的模式。 通过仅刷新必须保留数据的指定区域，可以减少刷新操作中的功耗，从而在掉电模式下大幅度地削减功耗。