公开(公告)号：US09859128B2

公开(公告)日：2018-01-02

申请号：US15337781

申请日：2016-10-28

Applicant: APPLIED MATERIALS, INC.

Inventor： Fei Wang ,  Mikhail Korolik ,  Nitin K. Ingle ,  Anchuan Wang ,  Robert Jan Visser

IPC: H01L21/311 ,  H01L21/461 ,  H01L21/02

CPC classification number: H01L21/31144 ,  C09D183/08 ,  H01J37/3244 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/0337 ,  H01L21/3105 ,  H01L21/31116

Abstract: Methods of etching silicon nitride faster than silicon or silicon oxide are described. Methods of selectively depositing additional material onto the silicon nitride are also described. Exposed portions of silicon nitride and silicon oxide may both be present on a patterned substrate. A self-assembled monolayer (SAM) is selectively deposited over the silicon oxide but not on the exposed silicon nitride. Molecules of the self-assembled monolayer include a head moiety and a tail moiety, the head moiety forming a bond with the OH group on the exposed silicon oxide portion and the tail moiety extending away from the patterned substrate. A subsequent exposure to an etchant or a deposition precursor may then be used to selectively remove silicon nitride or to selectively deposit additional material on the silicon nitride.

公开(公告)号：US20170229293A1

公开(公告)日：2017-08-10

申请号：US15581425

申请日：2017-04-28

Applicant: Applied Materials, Inc.

Inventor： Soonam Park ,  Yufei Zhu ,  Edwin C. Suarez ,  Nitin K. Ingle ,  Dmitry Lubomirsky ,  Jiayin Huang

IPC: H01J37/32 ,  H01L21/3213 ,  C23C16/455 ,  H01L21/66 ,  C23C16/505 ,  C23C16/52 ,  H01L21/311 ,  H01L21/67

Abstract: A method of conditioning internal surfaces of a plasma source includes flowing first source gases into a plasma generation cavity of the plasma source that is enclosed at least in part by the internal surfaces. Upon transmitting power into the plasma generation cavity, the first source gases ignite to form a first plasma, producing first plasma products, portions of which adhere to the internal surfaces. The method further includes flowing the first plasma products out of the plasma generation cavity toward a process chamber where a workpiece is processed by the first plasma products, flowing second source gases into the plasma generation cavity. Upon transmitting power into the plasma generation cavity, the second source gases ignite to form a second plasma, producing second plasma products that at least partially remove the portions of the first plasma products from the internal surfaces.

公开(公告)号：US09607856B2

公开(公告)日：2017-03-28

申请号：US14720183

申请日：2015-05-22

Applicant: Applied Materials, Inc.

Inventor： Xikun Wang ,  Anchuan Wang ,  Nitin K. Ingle ,  Dmitry Lubomirsky

IPC: H01L21/3213 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/28 ,  H01L21/48 ,  H01J37/32

CPC classification number: H01L21/32136 ,  H01J37/32357 ,  H01J37/3244 ,  H01L21/02068 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/32135 ,  H01L21/4814

Abstract: Methods are described herein for selectively etching titanium nitride relative to dielectric films, which may include, for example, alternative metals and metal oxides lacking in titanium and/or silicon-containing films (e.g. silicon oxide, silicon carbon nitride and low-K dielectric films). The methods include a remote plasma etch formed from a chlorine-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the titanium nitride. The plasma effluents react with exposed surfaces and selectively remove titanium nitride while very slowly removing the other exposed materials. The substrate processing region may also contain a plasma to facilitate breaking through any titanium oxide layer present on the titanium nitride. The plasma in the substrate processing region may be gently biased relative to the substrate to enhance removal rate of the titanium oxide layer.

公开(公告)号：US09583333B2

公开(公告)日：2017-02-28

申请号：US14520721

申请日：2014-10-22

Applicant: Applied Materials, Inc.

Inventor： Amit Chatterjee ,  Abhijit Basu Mallick ,  Nitin K. Ingle

IPC: H01L21/02 ,  C23C16/34 ,  C23C16/44 ,  C23C16/452 ,  C23C16/455

CPC classification number: H01L21/0217 ,  C23C16/345 ,  C23C16/4411 ,  C23C16/452 ,  C23C16/45582 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/02222 ,  H01L21/02274

Abstract: Embodiments of the present invention generally provide methods for forming a silicon nitride layer on a substrate. In one embodiment, a method of forming a silicon nitride layer using remote plasma chemical vapor deposition (CVD) at a temperature that is less than 300 degrees Celsius is disclosed. The precursors for the remote plasma CVD process include tris(dimethylamino)silane (TRIS), dichlorosilane (DCS), trisilylamine (TSA), bis-t-butylaminosilane (BTBAS), hexachlorodisilane (HCDS) or hexamethylcyclotrisilazane (HMCTZ).

Abstract translation: 本发明的实施方案通常提供在衬底上形成氮化硅层的方法。 在一个实施例中，公开了在小于300摄氏度的温度下使用远程等离子体化学气相沉积（CVD）形成氮化硅层的方法。 用于远程等离子体CVD工艺的前体包括三（二甲基氨基）硅烷（TRIS），二氯硅烷（DCS），三甲基胺（TSA），双 - 叔丁基氨基硅烷（BTBAS），六氯二硅烷（HCDS）或六甲基环三硅氮烷（HMCTZ）。

公开(公告)号：US09576815B2

公开(公告)日：2017-02-21

申请号：US14690165

申请日：2015-04-17

Applicant: Applied Materials, Inc.

Inventor： Jingjing Xu ,  Fei Wang ,  Anchuan Wang ,  Nitin K. Ingle ,  Robert Jan Visser

IPC: H01L21/302 ,  H01L21/311

CPC classification number: H01L21/31116

Abstract: A method of etching silicon nitride on patterned heterogeneous structures is described and includes a gas phase etch using anhydrous vapor-phase HF. The HF may be combined with one or more of several precursors in the substrate processing region and near the substrate to increase the silicon nitride etch rate and/or the silicon nitride selectivity. The silicon nitride etch selectivity is increased most notably when compared with silicon of various forms. No precursors are excited in any plasma either outside or inside the substrate processing region according to embodiments. The HF may be flowed through one set of channels in a dual-channel showerhead while the other precursor is flowed through a second set of channels in the dual-channel showerhead.

Abstract translation: 描述了在图案化异质结构上蚀刻氮化硅的方法，并且包括使用无水气相HF的气相蚀刻。 HF可以与衬底处理区域和衬底附近的几种前体中的一种或多种组合以增加氮化硅蚀刻速率和/或氮化硅选择性。 当与各种形式的硅相比时，氮化硅蚀刻选择性最显着地增加。 根据实施例，在衬底处理区域的外部或内部，在任何等离子体中都不会激发前体。 HF可以在双通道喷头中流过一组通道，而另一个前体流经双通道喷头中的第二组通道。

公开(公告)号：US09576788B2

公开(公告)日：2017-02-21

申请号：US14695392

申请日：2015-04-24

Applicant: Applied Materials, Inc.

Inventor： Jie Liu ,  Seung Park ,  Anchuan Wang ,  Zhenjiang Cui ,  Nitin K. Ingle

IPC: H01L21/02 ,  H01L21/311 ,  H01L27/115 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/308

CPC classification number: H01L21/02057 ,  H01L21/02063 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/0262 ,  H01L21/0273 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32137 ,  H01L27/11556 ,  H01L27/11582

Abstract: A method of removing an amorphous silicon/silicon oxide film stack from vias is described. The method may involve a remote plasma comprising fluorine and a local plasma comprising fluorine and a nitrogen-and-hydrogen-containing precursor unexcited in the remote plasma to remove the silicon oxide. The method may then involve a local plasma of inert species to potentially remove any thin carbon layer (leftover from the photoresist) and to treat the amorphous silicon layer in preparation for removal. The method may then involve removal of the treated amorphous silicon layer with several options possibly within the same substrate processing region. The bottom of the vias may then possess exposed single crystal silicon which is conducive to epitaxial single crystal silicon film growth. The methods presented herein may be particularly well suited for 3d NAND (e.g. VNAND) device formation.

Abstract translation: 描述了从通孔去除非晶硅/氧化硅膜堆叠的方法。 该方法可以包括远程等离子体，其包含氟和包含氟的局部等离子体和在远程等离子体中未喷射的含氮和氢的前体以除去氧化硅。 该方法可以包括惰性物质的局部等离子体，以潜在去除任何薄碳层（从光致抗蚀剂残留），并处理非晶硅层以准备去除。 该方法然后可以包括可能在相同的衬底处理区域内的几个选项去除经处理的非晶硅层。 然后，通孔的底部可以具有有利于外延单晶硅膜生长的暴露的单晶硅。 本文给出的方法可能特别适用于3d NAND（例如VNAND）器件形成。

公开(公告)号：US09564341B1

公开(公告)日：2017-02-07

申请号：US14818165

申请日：2015-08-04

Applicant: Applied Materials, Inc.

Inventor： Jingjing Xu ,  Anchuan Wang ,  Nitin K. Ingle

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/311

CPC classification number: H01L21/31116 ,  H01J37/32357

Abstract: A method of etching silicon oxide on patterned heterogeneous structures is described and includes a gas phase etch using anhydrous vapor-phase HF. The HF is combined with an additional precursor in the substrate processing region. The HF may enter through one channel(s) and the additional precursor may flow through another channel(s) prior to forming the combination. The combination may be formed near the substrate. The silicon oxide etch selectivity relative to silicon nitride from is selectable from about one to several hundred. In all cases, the etch rate of exposed silicon, if present, is negligible. No precursors are excited in any plasma either outside or inside the substrate processing region according to embodiments. The additional precursor may be a nitrogen-and-hydrogen-containing precursor such as ammonia.

Abstract translation: 描述了在图案化的异质结构上蚀刻氧化硅的方法，并且包括使用无水气相HF的气相蚀刻。 HF与衬底处理区域中的另外的前体结合。 在形成组合之前，HF可以通过一个通道进入，另外的前体可以流过另一个通道。 可以在衬底附近形成组合。 相对于氮化硅的氧化硅蚀刻选择性可以从大约一百到几百个来选择。 在所有情况下，暴露的硅的蚀刻速率（如果存在）是可忽略的。 根据实施例，在衬底处理区域的外部或内部，在任何等离子体中都不会激发前体。 另外的前体可以是含氮和氢的前体，例如氨。

公开(公告)号：US20170018439A1

公开(公告)日：2017-01-19

申请号：US14801542

申请日：2015-07-16

Applicant: Applied Materials, Inc.

Inventor： Xikun Wang ,  David Cui ,  Anchuan Wang ,  Nitin K. Ingle

IPC: H01L21/3213 ,  H01L21/768

CPC classification number: H01L21/32138 ,  H01J37/32449 ,  H01L21/02071 ,  H01L21/3065 ,  H01L21/31122 ,  H01L21/32135 ,  H01L21/32136 ,  H01L21/7684

Abstract: Methods are described for etching metal layers that are difficult to volatize, such as cobalt, nickel, and platinum to form an etched metal layer with reduced surface roughness. The methods include pretreating the metal layer with a local plasma formed from a hydrogen-containing precursor. The pretreated metal layer is then reacted with a halogen-containing precursor to form a halogenated metal layer having a halogenated etch product. A carbon-and-nitrogen-containing precursor reacts with the halogenated etch product to form a volatile etch product that can be removed in the gas phase from the etched surface of the metal layer. The surface roughness may be reduced by performing one or more plasma treatments on the etching metal layer after a plurality of etching sequences. Surface roughness is also reduced by controlling the temperature and length of time the metal layer is reacting with the etchant precursors.

Abstract translation: 描述了用于蚀刻难以挥发的金属层（例如钴，镍和铂）以形成具有降低的表面粗糙度的蚀刻金属层的方法。 所述方法包括用由含氢前体形成的局部等离子体预处理金属层。 然后将预处理的金属层与含卤素的前体反应以形成具有卤化蚀刻产物的卤化金属层。 含氮和氮的前体与卤化蚀刻产物反应以形成挥发性蚀刻产物，其可以在气相中从金属层的蚀刻表面除去。 通过在多个蚀刻顺序之后对蚀刻金属层进行一次或多次等离子体处理，可以减少表面粗糙度。 通过控制金属层与蚀刻剂前体反应的时间的温度和长度也可以减少表面粗糙度。

公开(公告)号：US09496167B2

公开(公告)日：2016-11-15

申请号：US14448059

申请日：2014-07-31

Applicant: Applied Materials, Inc.

Inventor： Vinod R. Purayath ,  Randhir Thakur ,  Shankar Venkataraman ,  Nitin K. Ingle

IPC: H01L21/764 ,  H01L27/115 ,  H01L21/311 ,  H01L29/06 ,  H01L21/28 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/764 ,  H01J37/32357 ,  H01L21/02071 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31116 ,  H01L21/67069 ,  H01L21/67103 ,  H01L21/68764 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66833 ,  H01L29/7887

Abstract: Methods of forming flash memory cells are described which incorporate air gaps for improved performance. The methods are useful for so-called “2-d flat cell” flash architectures. 2-d flat cell flash memory involves a reactive ion etch to dig trenches into multi-layers containing high work function and other metal layers. The methods described herein remove the metal oxide debris from the sidewalls of the multi-layer trench and then, without breaking vacuum, selectively remove shallow trench isolation (STI) oxidation which become the air gaps. Both the metal oxide removal and the STI oxidation removal are carried out in the same mainframe with highly selective etch processes using remotely excited fluorine plasma effluents.

Abstract translation: 描述形成闪速存储器单元的方法，其包括用于改善性能的气隙。 这些方法对于所谓的“2-d平坦单元”闪存架构是有用的。 2-d平板电池闪存包括反应离子蚀刻，以将沟槽挖掘成包含高功函数和其它金属层的多层。 本文描述的方法从多层沟槽的侧壁去除金属氧化物碎屑，然后在不破坏真空的情况下选择性地去除成为气隙的浅沟槽隔离（STI）氧化。 金属氧化物去除和STI氧化去除都是使用远程激发的氟等离子体流出物，在相同的主机中进行高选择性蚀刻工艺。

公开(公告)号：US20160314961A1

公开(公告)日：2016-10-27

申请号：US14695392

申请日：2015-04-24

Applicant: APPLIED MATERIALS, INC.

Inventor： Jie Liu ,  Seung Park ,  Anchuan Wang ,  Zhenjiang Cui ,  Nitin K. Ingle

IPC: H01L21/02 ,  H01L27/115 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/308

CPC classification number: H01L21/02057 ,  H01L21/02063 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/0262 ,  H01L21/0273 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32137 ,  H01L27/11556 ,  H01L27/11582

Abstract: A method of removing an amorphous silicon/silicon oxide film stack from vias is described. The method may involve a remote plasma comprising fluorine and a local plasma comprising fluorine and a nitrogen-and-hydrogen-containing precursor unexcited in the remote plasma to remove the silicon oxide. The method may then involve a local plasma of inert species to potentially remove any thin carbon layer (leftover from the photoresist) and to treat the amorphous silicon layer in preparation for removal. The method may then involve removal of the treated amorphous silicon layer with several options possibly within the same substrate processing region. The bottom of the vias may then possess exposed single crystal silicon which is conducive to epitaxial single crystal silicon film growth. The methods presented herein may be particularly well suited for 3d NAND (e.g. VNAND) device formation.

Abstract translation: 描述了从通孔去除非晶硅/氧化硅膜堆叠的方法。 该方法可以包括远程等离子体，其包含氟和包含氟的局部等离子体和在远程等离子体中未喷射的含氮和氢的前体以除去氧化硅。 该方法可以包括惰性物质的局部等离子体，以潜在去除任何薄碳层（从光致抗蚀剂残留），并处理非晶硅层以准备去除。 该方法然后可以包括可能在相同的衬底处理区域内的几个选项去除经处理的非晶硅层。 然后，通孔的底部可以具有有利于外延单晶硅膜生长的暴露的单晶硅。 本文给出的方法可能特别适用于3d NAND（例如VNAND）器件形成。