公开(公告)号：US20070267745A1

公开(公告)日：2007-11-22

申请号：US11437726

申请日：2006-05-22

申请人： Clinton Chao ,  Pei-Haw Tsao ,  Szu Wei Lu ,  Tjandra Winata Karta

发明人： Clinton Chao ,  Pei-Haw Tsao ,  Szu Wei Lu ,  Tjandra Winata Karta

IPC分类号： H01L29/40 ,  H01L21/44

CPC分类号： H01L24/12 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05016 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05099

摘要： A semiconductor device and method of manufacturing are provided that include forming an electrically conductive bump on a substrate and forming at least one passivation layer on the bump to reduce solder joint failures.

摘要翻译： 提供了半导体器件和制造方法，其包括在衬底上形成导电凸块并且在凸起上形成至少一个钝化层以减少焊点失效。

公开(公告)号：US20070267724A1

公开(公告)日：2007-11-22

申请号：US11435436

申请日：2006-05-16

申请人： Shin-Puu Jeng ,  Clinton Chao ,  Szu Wei Lu

发明人： Shin-Puu Jeng ,  Clinton Chao ,  Szu Wei Lu

IPC分类号： H01L23/58 ,  H01L21/46

CPC分类号： H01L23/562 ,  H01L21/02123 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/302 ,  H01L21/314 ,  H01L21/316 ,  H01L21/3185 ,  H01L21/563 ,  H01L21/78 ,  H01L23/52 ,  H01L23/585 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01327 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 μm, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.

摘要翻译： 通过在衬底的表面上形成的薄膜补偿施加在衬底上的应力来减小集成电路衬底的翘曲和断裂。 对于厚度基本上小于约150μm的衬底特别有利的是，在衬底的表面上形成应力调节层，以基本上抵消或平衡衬底中的应力，否则会导致衬底弯曲。 衬底包括在第一表面上的多个接合焊盘，用于与其它部件电连接。

公开(公告)号：US20110097893A1

公开(公告)日：2011-04-28

申请号：US12983967

申请日：2011-01-04

申请人： Shin-Puu Jeng ,  Clinton Chao ,  Szu Wei Lu

发明人： Shin-Puu Jeng ,  Clinton Chao ,  Szu Wei Lu

IPC分类号： H01L21/31 ,  H01L21/768

CPC分类号： H01L23/562 ,  H01L21/02123 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/302 ,  H01L21/314 ,  H01L21/316 ,  H01L21/3185 ,  H01L21/563 ,  H01L21/78 ,  H01L23/52 ,  H01L23/585 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01327 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 μm, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.

摘要翻译： 通过在衬底的表面上形成的薄膜补偿施加在衬底上的应力来减小集成电路衬底的翘曲和断裂。 对于厚度基本上小于约150μm的衬底特别有利的是，在衬底的表面上形成应力调节层，以基本上抵消或平衡衬底中的应力，否则会使衬底弯曲。 衬底包括在第一表面上的多个接合焊盘，用于与其它部件电连接。

公开(公告)号：US07880278B2

公开(公告)日：2011-02-01

申请号：US11435436

申请日：2006-05-16

申请人： Shin-Puu Jeng ,  Clinton Chao ,  Szu Wei Lu

发明人： Shin-Puu Jeng ,  Clinton Chao ,  Szu Wei Lu

IPC分类号： H01L23/495

CPC分类号： H01L23/562 ,  H01L21/02123 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/302 ,  H01L21/314 ,  H01L21/316 ,  H01L21/3185 ,  H01L21/563 ,  H01L21/78 ,  H01L23/52 ,  H01L23/585 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01327 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 μm, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.

摘要翻译： 通过在衬底的表面上形成的薄膜补偿施加在衬底上的应力来减小集成电路衬底的翘曲和断裂。 对于厚度基本上小于约150μm的衬底特别有利的是，在衬底的表面上形成应力调节层，以基本上抵消或平衡衬底中的应力，否则会使衬底弯曲。 衬底包括在第一表面上的多个接合焊盘，用于与其它部件电连接。

公开(公告)号：US07851916B2

公开(公告)日：2010-12-14

申请号：US11082675

申请日：2005-03-17

申请人： Hsin-Hui Lee ,  Mickey Ken ,  Chien-Hsiun Lee ,  Szu Wei Lu

发明人： Hsin-Hui Lee ,  Mickey Ken ,  Chien-Hsiun Lee ,  Szu Wei Lu

IPC分类号： H01L21/20

CPC分类号： H01L21/563 ,  H01L23/3128 ,  H01L24/28 ,  H01L24/81 ,  H01L29/045 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/0401

摘要： A method and system is disclosed for better packaging semiconductor devices. In one example, a semiconductor device package comprises a package substrate, at least one die with an orientation of placed on the substrate with electrical connections made between the package substrate and the die, and an underfill fillet attaching the die to the substrate with the underfill fillet reaching less than 60% of a thickness of the die on at least one side thereof.

摘要翻译： 公开了一种用于更好地封装半导体器件的方法和系统。 在一个示例中，半导体器件封装包括封装衬底，至少一个具有取向<100>的裸片放置在衬底上，其中在封装衬底和裸片之间形成电连接，以及将裸片附接到衬底 其中底部填充圆角在其至少一侧上达到小于模具厚度的60％。

公开(公告)号：US07427803B2

公开(公告)日：2008-09-23

申请号：US11525603

申请日：2006-09-22

申请人： Clinton Chao ,  Chao-Shun Hsu ,  Mark Shane Peng ,  Szu Wei Lu ,  Tjandra Winata Karta

发明人： Clinton Chao ,  Chao-Shun Hsu ,  Mark Shane Peng ,  Szu Wei Lu ,  Tjandra Winata Karta

IPC分类号： H01L23/552 ,  H01L23/58

CPC分类号： H01L25/0657 ,  H01L21/76 ,  H01L21/823481 ,  H01L23/481 ,  H01L23/585 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/014 ,  H01L2924/013 ,  H01L2924/00014

摘要： An isolation structure for electromagnetic interference includes a semiconductor substrate, a first integrated circuit in the semiconductor substrate, a second integrated circuit in the semiconductor substrate, and an isolation structure in a direct path between the first and the second integrated circuits, wherein the isolation structure comprises a through-silicon via.

摘要翻译： 用于电磁干扰的隔离结构包括半导体衬底，半导体衬底中的第一集成电路，半导体衬底中的第二集成电路以及第一和第二集成电路之间的直接路径中的隔离结构，其中隔离结构 包括通硅通孔。

公开(公告)号：US20080023850A1

公开(公告)日：2008-01-31

申请号：US11493375

申请日：2006-07-26

申请人： Szu Wei Lu ,  Clinton Chao ,  Ann Luh ,  Tjandra Winata Karta ,  Jerry Tzou ,  Kuo-Chin Chang

发明人： Szu Wei Lu ,  Clinton Chao ,  Ann Luh ,  Tjandra Winata Karta ,  Jerry Tzou ,  Kuo-Chin Chang

IPC分类号： H01L23/48

CPC分类号： H01L23/147 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5386 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/157 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/0401

摘要： A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 μm. A plurality of through-hole vias are formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips.

摘要翻译： 硅基薄封装衬底用于封装半导体芯片。 硅基薄封装衬底优选具有小于约200μm的厚度。 在硅基薄封装衬底中形成多个通孔，连接BGA球和焊料凸块。 硅基薄封装衬底可以用作半导体芯片的载体。

公开(公告)号：US20080017956A1

公开(公告)日：2008-01-24

申请号：US11458479

申请日：2006-07-19

申请人： Szu Wei Lu ,  Jerry Tzou

发明人： Szu Wei Lu ,  Jerry Tzou

IPC分类号： H01L23/495

CPC分类号： H01L23/3107 ,  H01L21/76898 ,  H01L23/49513 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/66 ,  H01L24/05 ,  H01L24/06 ,  H01L24/12 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04026 ,  H01L2224/05026 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06517 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29339 ,  H01L2224/32237 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/83365 ,  H01L2224/83439 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00015

摘要： A semiconductor device includes a semiconductor substrate having top and bottom surfaces, the top surface having at least one device region thereon. At least one trench opening is formed through the substrate from the bottom surface and connecting to the device region. A layer of conductive material is deposited in the at least one trench opening and partially fills the trench opening. A layer of conductive adhesive is deposited over the layer of conductive material and fills a remaining portion of the trench opening.

摘要翻译： 半导体器件包括具有顶表面和底表面的半导体衬底，顶表面上具有至少一个器件区域。 至少一个沟槽开口从底表面穿过衬底形成并且连接到器件区域。 一层导电材料沉积在至少一个沟槽开口中并部分填充沟槽开口。 导电粘合剂层沉积在导电材料层上并填充沟槽开口的剩余部分。

公开(公告)号：US07265034B2

公开(公告)日：2007-09-04

申请号：US11174710

申请日：2005-07-05

申请人： Szu Wei Lu ,  Hsin-Hui Lee ,  Ming-Chung Sung ,  Mirng-Ji Lii

发明人： Szu Wei Lu ,  Hsin-Hui Lee ,  Ming-Chung Sung ,  Mirng-Ji Lii

IPC分类号： H01L21/46

CPC分类号： H01L21/78 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/13116 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A method of cutting an integrated circuit chip from a wafer having a plurality of integrated circuit chips is provided. An upper portion of the wafer is ablated using two laser beams to form two substantially parallel trenches that extend into the wafer from a top surface of the wafer through intermetal dielectric layers and at least partially into a substrate of the wafer. After the ablating to form the two trenches, cutting through the wafer between outer sidewalls of the two laser-ablated trenches with a saw blade is performed. A width between the outer sidewalls of the two laser-ablated trenches is greater than a cutting width of the saw blade. This may be particularly useful in lead-free packaging applications and/or applications where the intermetal dielectric layers use low-k dielectric materials, for example.

摘要翻译： 提供了从具有多个集成电路芯片的晶片切割集成电路芯片的方法。 使用两个激光束来消除晶片的上部，以形成两个基本上平行的沟槽，其从晶片的顶表面穿过金属间电介质层并且至少部分地延伸到晶片的衬底中延伸到晶片中。 在消融以形成两个沟槽之后，执行用锯片在两个激光烧蚀的沟槽的外侧壁之间切割晶片。 两个激光烧蚀沟槽的外侧壁之间的宽度大于锯片的切割宽度。 这对于例如在金属间电介质层使用低k电介质材料的无铅封装应用和/或应用中尤其有用。