公开(公告)号：US09595493B2

公开(公告)日：2017-03-14

申请号：US14822597

申请日：2015-08-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhiguo Sun ,  Qiang Fang ,  Huang Liu ,  Haigou Huang ,  Jiehui Shu ,  Jin Ping Liu

IPC: H01L21/76 ,  H01L23/528 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L21/321

CPC classification number: H01L23/528 ,  H01L21/3065 ,  H01L21/321 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76853 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53204 ,  H01L23/53238 ,  H01L23/53266

Abstract: Reducing liner corrosion during metallization of semiconductor devices at BEOL includes providing a starting metallization structure, the structure including a bottom layer of dielectric material with a via therein, a liner lining the via and extending over upper edges thereof, the lined via over filled with a conductive material, recessing the conductive material down to the liner, further selectively recessing the conductive material below the upper edges of the via without damaging the liner, and forming a cap of the liner material on the conductive material.

Abstract translation: 在BEOL的半导体器件的金属化期间减少衬里腐蚀包括提供起始金属化结构，该结构包括介电材料的底层，其中具有通孔，衬套衬套通孔并在其上边缘延伸的衬里，衬里通孔填充有 导电材料将导电材料向下凹入衬垫，进一步选择性地使导电材料在通孔的上边缘下方凹陷，而不损坏衬垫，并且在导电材料上形成衬垫材料的帽。

公开(公告)号：US09478625B1

公开(公告)日：2016-10-25

申请号：US14878440

申请日：2015-10-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi ,  Huang Liu

IPC: H01L21/00 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/43 ,  H01L21/8234 ,  H01L21/324 ,  H01L21/265 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823443 ,  H01L27/0629 ,  H01L28/24 ,  H01L29/66545

Abstract: A semiconductor structure includes a semiconductor substrate, fins coupled to the substrate and surrounded at a bottom portion thereof by isolation material, and resistor(s) situated in the gate region(s), the gate regions being filled with undoped dummy gate material. As part of a replacement gate process, the resistor(s) are realized by forming silicide over dummy gate material, i.e., the dummy gate material for the resistor(s) is not removed.

Abstract translation: 半导体结构包括：半导体衬底，耦合到衬底并且在其底部被隔离材料包围的鳍片以及位于栅极区域中的电阻器，栅极区域被未掺杂的虚拟栅极材料填充。 作为替代栅极处理的一部分，通过在伪栅极材料上形成硅化物，即不去除用于电阻器的虚拟栅极材料来实现电阻器。

公开(公告)号：US09443956B2

公开(公告)日：2016-09-13

申请号：US14675880

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Biao Zuo ,  Jin Ping Liu ,  Huang Liu

IPC: H01L29/66

CPC classification number: H01L29/6656 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a line feature above a substrate. Carbon-containing spacers are formed on sidewalls of the line feature. A first dielectric layer is formed above the carbon spacers and the line feature. The first dielectric layer is planarized to expose upper ends of the carbon-containing spacers. An ashing process is performed to remove the carbon-containing spacers and define air gaps adjacent the line feature. A cap layer is formed to seal the upper ends of the air gaps.

Abstract translation: 一种方法包括在衬底上形成线特征。 含碳隔离物形成在线特征的侧壁上。 第一电介质层形成在碳间隔物和线特征之上。 平面化第一介电层以暴露含碳间隔物的上端。 执行灰化处理以除去含碳间隔物并限定与线特征相邻的气隙。 形成盖层以密封气隙的上端。

公开(公告)号：US09418832B2

公开(公告)日：2016-08-16

申请号：US14624786

申请日：2015-02-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hung-Wei Liu ,  Tsung-Liang Chen ,  Huang Liu ,  Zhiguo Sun

IPC: H01L21/302 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L21/02112 ,  H01L21/02129 ,  H01L21/02131 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/02337 ,  H01L21/76837

Abstract: A method for flowable oxide deposition is provided. An oxygen source gas is increased as a function of time or film depth to change the flowable oxide properties such that the deposited film is optimized for gap fill near a substrate surface where high aspect ratio shapes are present. The oxygen gas flow rate increases as the film depth increases, such that the deposited film is optimized for planarization quality at the upper regions of the deposited film.

公开(公告)号：US20160163816A1

公开(公告)日：2016-06-09

申请号：US14675880

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Biao Zuo ,  Jin Ping Liu ,  Huang Liu

IPC: H01L29/66

CPC classification number: H01L29/6656 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a line feature above a substrate. Carbon-containing spacers are formed on sidewalls of the line feature. A first dielectric layer is formed above the carbon spacers and the line feature. The first dielectric layer is planarized to expose upper ends of the carbon-containing spacers. An ashing process is performed to remove the carbon-containing spacers and define air gaps adjacent the line feature. A cap layer is formed to seal the upper ends of the air gaps.

Abstract translation: 一种方法包括在衬底上形成线特征。 含碳隔离物形成在线特征的侧壁上。 第一电介质层形成在碳间隔物和线特征之上。 平面化第一介电层以暴露含碳间隔物的上端。 执行灰化处理以除去含碳间隔物并限定与线特征相邻的气隙。 形成盖层以密封气隙的上端。

公开(公告)号：US09349635B2

公开(公告)日：2016-05-24

申请号：US13770464

申请日：2013-02-19

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： San Leong Liew ,  Huang Liu

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76816 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods of forming integrated circuits are provided. A method of forming an integrated circuit includes providing a substrate that includes an electrical contact disposed therein. A first dielectric layer is formed over the substrate and electrical contact. A metal-containing layer is patterned over the first dielectric layer, with at least a first portion of the patterned metal-containing layer disposed over the first dielectric layer. The patterned metal-containing layer is absent in regions of the first dielectric layer over the electrical contact. A second dielectric layer is formed over the patterned metal-containing layer. A first via is etched in the first dielectric layer and the second dielectric layer over the electrical contact, and a second via is etched in the second dielectric layer over the patterned metal-containing layer. The first via and the second via are filled with an electrically-conductive material.

Abstract translation: 提供了形成集成电路的集成电路和方法。 形成集成电路的方法包括提供包括设置在其中的电接触的基板。 第一电介质层形成在衬底上并进行电接触。 在第一介电层上图案化含金属层，其中图案化的含金属层的至少第一部分设置在第一介电层上。 在电触点上的第一介电层的区域中不存在图案化的含金属层。 在图案化的含金属层上形成第二介电层。 在第一电介质层和第二电介质层上蚀刻第一通孔，并且在图案化的含金属层上的第二介电层中蚀刻第二通孔。 第一通孔和第二通孔被填充有导电材料。

公开(公告)号：US09329471B1

公开(公告)日：2016-05-03

申请号：US14533497

申请日：2014-11-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang Ning ,  Xintuo Dai ,  Huang Liu ,  Chin Teong Lim

IPC: G03F1/54 ,  G03F1/70 ,  G03F1/80 ,  G03F7/20 ,  G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/54 ,  G03F1/70 ,  G03F1/80 ,  G03F7/16 ,  G03F7/20 ,  G03F7/32 ,  G03F7/34

Abstract: Achieving a critical dimension target for a feature based on characteristics of a resist is facilitated. Mask data is established for fabricating a lithographic mask to expose different regions of a resist to high, low, and intermediate exposure levels. The resist is configured to exhibit high solubility when exposed to the high or low exposure level, and low solubility when exposed to the intermediate exposure level. A critical dimension for a region of the resist to be exposed to the intermediate exposure level is determined, and the mask data is established to indicate opaque regions for forming on the lithographic mask. The opaque regions are arrayed to facilitate exposing the region of the resist to the intermediate exposure level, to achieve the determined critical dimension. Further, a method is provided for forming in-situ a patterned mask from a mask layer above a substrate material.

Abstract translation: 实现基于抗蚀剂特性的特征的关键尺寸目标。 建立掩模数据用于制造光刻掩模以将抗蚀剂的不同区域暴露于高，低和中等曝光水平。 抗蚀剂被配置为当暴露于高或低曝光水平时表现出高溶解度，并且当暴露于中等曝光水平时具有低溶解度。 确定抗蚀剂暴露于中间曝光水平的区域的关键尺寸，并且建立掩模数据以指示用于在光刻掩模上形成的不透明区域。 排列不透明区域以便于将抗蚀剂的区域暴露于中间曝光水平，以获得确定的临界尺寸。 此外，提供了一种用于从衬底材料上方的掩模层原位形成图案化掩模的方法。

公开(公告)号：US09305832B2

公开(公告)日：2016-04-05

申请号：US14315659

申请日：2014-06-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiang Hu ,  Yuping Ren ,  Duohui Bei ,  Sipeng Gu ,  Huang Liu

IPC: H01L21/308 ,  H01L21/768 ,  H01L21/033 ,  H01L23/538 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/76816 ,  H01L21/02063 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods are provided for dimension-controlled via formation over a circuit structure, including over multiple adjacent conductive structures. The method(s) includes, for instance, providing a patterned multi-layer stack structure above the circuit structure, the stack structure including at least one layer, and a pattern transfer layer above the at least one layer, the pattern transfer layer being patterned with at least one via opening; providing a sidewall spacer layer within the at least one via opening to form at least one dimension-controlled via opening; and etching through the at least one layer of the stack structure using the at least one dimension-controlled via opening to facilitate providing the via(s) over the circuit structure. In one implementation, the stack structure includes a trench-opening within a patterned hard mask layer disposed between a dielectric layer and a planarization layer, and the via(s) is partially self-aligned to the trench.

Abstract translation: 提供了用于在电路结构上的尺寸控制的通孔形成的方法，包括在多个相邻的导电结构上。 所述方法包括例如在电路结构之上提供图案化的多层堆叠结构，所述堆叠结构包括至少一层，以及在所述至少一层上方的图案转移层，所述图案转移层被图案化 至少有一个通孔; 在所述至少一个通孔开口内提供侧壁间隔层，以形成至少一个尺寸控制的通孔开口; 以及使用所述至少一个尺寸控制的通孔开口蚀刻穿过所述堆叠结构的所述至少一个层，以便于在所述电路结构上提供通孔。 在一个实施方案中，堆叠结构包括设置在电介质层和平坦化层之间的图案化硬掩模层内的沟槽开口，并且通孔部分地自对准沟槽。

公开(公告)号：US09230863B2

公开(公告)日：2016-01-05

申请号：US14177854

申请日：2014-02-11

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jialin Yu ,  Huang Liu ,  Jilin Xia ,  Girish Bohra

IPC: H01L21/4763 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/823437 ,  H01L21/823456 ,  H01L21/823475 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Integrated circuits with tungsten components having a smooth surface and methods for producing such integrated circuits are provided. A method of producing the integrated circuits includes forming a nucleation layer overlying a substrate and within a cavity, where the nucleation layer includes tungsten. A nucleation layer thickness is reduced, and a fill layer if formed overlying the nucleation layer.

Abstract translation: 提供具有光滑表面的钨成分的集成电路以及用于制造这种集成电路的方法。 一种制造集成电路的方法包括形成层叠在基底上的成核层，并且其中成核层包含钨。 成核层厚度减小，填充层如果形成在成核层上方。

公开(公告)号：US09230822B1

公开(公告)日：2016-01-05

申请号：US14306920

申请日：2014-06-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Haigou Huang ,  Jin Ping Liu ,  Huang Liu

IPC: H01L21/3105 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/31055 ,  H01L21/02318 ,  H01L21/02326 ,  H01L21/0234 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/823821 ,  H01L21/823842

Abstract: A semiconductor structure with mixed n-type and p-type non-planar transistors includes a residual overlapping mask bump on one or more of the dummy gates. A dielectric layer is created over the structure having a top surface above the residual bump, for example, using a blanket deposition and chemical-mechanical underpolish (i.e., stopping before exposing the gate cap). The residual bump is then transformed into a same material as the dielectric, either in its entirety and then removing the combined dielectric, or by removing the dielectric first and partly removing the residual bump, the remainder of which is then transformed and the dielectric removed. In either case, the structure is planarized for further processing.

Abstract translation: 具有混合n型和p型非平面晶体管的半导体结构包括在一个或多个虚拟栅极上的残留重叠掩模凸块。 例如，使用覆盖沉积和化学机械的低估（即，在暴露栅极盖之前停止），在该结构上方形成介电层，该顶表面具有顶部表面。 然后将剩余的凸块转变成与电介质完全相同的材料，然后去除组合的电介质，或者通过首先去除电介质并部分去除残余凸块，然后将其余部分转化并除去电介质。 在任一种情况下，将结构平坦化用于进一步处理。