公开(公告)号：US20140054780A1

公开(公告)日：2014-02-27

申请号：US13591055

申请日：2012-08-21

Applicant: Edward Fuergut ,  Irmgard Escher-Poeppel ,  Gottfried Beer

Inventor： Edward Fuergut ,  Irmgard Escher-Poeppel ,  Gottfried Beer

IPC: H01L21/50 ,  H01L23/498

CPC classification number: H01L21/50 ,  H01L21/561 ,  H01L21/568 ,  H01L23/498 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/18 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/96 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/82104 ,  H01L2224/96 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2224/82 ,  H01L2924/00

Abstract: A number of semiconductor chips each include a first main face and a second main face opposite from the first main face. The second main face includes at least one electrical contact element. The semiconductor chips are placed on a carrier. A material layer is applied into intermediate spaces between adjacent semiconductor chips. The carrier is removed and a first electrical contact layer is applied to the first main faces of the semiconductor chips so that the electrical contact layer is electrically connected with each one of the electrical contact elements.

Abstract translation: 多个半导体芯片各自包括与第一主面相对的第一主面和第二主面。 第二主面包括至少一个电接触元件。 将半导体芯片放置在载体上。 将材料层施加到相邻半导体芯片之间的中间空间。 移除载体并且将第一电接触层施加到半导体芯片的第一主面，使得电接触层与每个电接触元件电连接。

公开(公告)号：US20140042603A1

公开(公告)日：2014-02-13

申请号：US13570783

申请日：2012-08-09

Applicant: Khalil Hosseini ,  Joachim Mahler ,  Ivan Nikitin ,  Gottfried Beer

Inventor： Khalil Hosseini ,  Joachim Mahler ,  Ivan Nikitin ,  Gottfried Beer

IPC: B23K1/20 ,  H01L23/48 ,  H01L21/78 ,  H01L23/495

CPC classification number: H01L24/27 ,  H01L23/14 ,  H01L23/49579 ,  H01L23/49883 ,  H01L24/05 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/04026 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05618 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/2741 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/29309 ,  H01L2224/29311 ,  H01L2224/29318 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/32245 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/8382 ,  H01L2224/8384 ,  H01L2224/83856 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/00

Abstract: A semiconductor device includes an electrically conducting carrier and a semiconductor chip disposed over the carrier. The semiconductor device also includes a porous diffusion solder layer provided between the carrier and the semiconductor chip.

Abstract translation: 半导体器件包括导电载体和设置在载体上的半导体芯片。 半导体器件还包括设置在载体和半导体芯片之间的多孔扩散焊料层。

公开(公告)号：US08598709B2

公开(公告)日：2013-12-03

申请号：US12871939

申请日：2010-08-31

Applicant: Thorsten Meyer ,  Gottfried Beer ,  Christian Geissler ,  Thomas Ort ,  Klaus Pressel ,  Bernd Waidhas ,  Andreas Wolter

Inventor： Thorsten Meyer ,  Gottfried Beer ,  Christian Geissler ,  Thomas Ort ,  Klaus Pressel ,  Bernd Waidhas ,  Andreas Wolter

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/5389 ,  H01L21/568 ,  H01L24/05 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L25/0655 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05547 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/18162 ,  H01L2924/00

Abstract: A method and a system for routing electrical connections are disclosed. A semiconductor device includes a first semiconductor chip and a routing plane having a plurality of routing lines. A first connecting line is electrically coupled to the first semiconductor chip and one of the plurality of routing lines and a second connecting line is electrically coupled to the one of the plurality of routing lines and to one of a second semiconductor chip or a first external contact element.

Abstract translation: 公开了用于路由电连接的方法和系统。 半导体器件包括第一半导体芯片和具有多个布线线路的布线平面。 第一连接线电耦合到第一半导体芯片，并且多个布线线之一和第二连接线电耦合到多个路由线中的一个并且耦合到第二半导体芯片或第一外部触点之一 元件。

公开(公告)号：US20120319298A1

公开(公告)日：2012-12-20

申请号：US13570986

申请日：2012-08-09

Applicant: Gottfried Beer ,  Irmgard Escher-Poeppel

Inventor： Gottfried Beer ,  Irmgard Escher-Poeppel

IPC: H01L21/50 ,  H01L23/522

CPC classification number: H01L24/96 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76879 ,  H01L23/3128 ,  H01L24/18 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/2919 ,  H01L2224/83856 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2924/0665 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.

Abstract translation: 公开了一种制造半导体芯片模块和半导体芯片封装的方法。 一个实施例提供第一层，第二层和基层。 第一层设置在基层上，第二层设置在第一层上。 多个半导体芯片被施加在第二层上方，并且具有施加的半导体芯片的第二层与第一层分离。

公开(公告)号：US20120258571A1

公开(公告)日：2012-10-11

申请号：US13529315

申请日：2012-06-21

Applicant: Gottfried Beer ,  Irmgard Escher-Poeppel

Inventor： Gottfried Beer ,  Irmgard Escher-Poeppel

IPC: H01L21/50

CPC classification number: H01L24/96 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76879 ,  H01L23/3128 ,  H01L24/18 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/2919 ,  H01L2224/83856 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2924/0665 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.

公开(公告)号：US08072071B2

公开(公告)日：2011-12-06

申请号：US12389103

申请日：2009-02-19

Applicant: Rainer Steiner ,  Jens Pohl ,  Werner Robl ,  Markus Brunnbauer ,  Gottfried Beer

Inventor： Rainer Steiner ,  Jens Pohl ,  Werner Robl ,  Markus Brunnbauer ,  Gottfried Beer

IPC: H01L23/498

CPC classification number: H01L23/528 ,  H01L21/561 ,  H01L21/568 ,  H01L23/5283 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/02351 ,  H01L2224/03462 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05006 ,  H01L2224/05012 ,  H01L2224/05017 ,  H01L2224/05546 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/00

Abstract: A semiconductor device includes a chip comprising a contact element, a structured dielectric layer over the chip, and a conductive element coupled to the contact element. The conductive element comprises a first portion embedded in the structured dielectric layer, a second portion at least partially spaced apart from the first portion and embedded in the structured dielectric layer, and a third portion contacting a top of the structured dielectric layer and extending at least vertically over the first portion and the second portion.

Abstract translation: 半导体器件包括芯片，其包括接触元件，芯片上方的结构化介电层以及耦合到接触元件的导电元件。 导电元件包括​​嵌入结构化电介质层中的第一部分，与第一部分至少部分间隔开并嵌入结构化介电层的第二部分，以及接触结构化介电层顶部并至少延伸的第三部分 垂直于第一部分和第二部分。

公开(公告)号：US20110291256A1

公开(公告)日：2011-12-01

申请号：US12791443

申请日：2010-06-01

Applicant: Rainer Steiner ,  Jens Pohl ,  Werner Robl ,  Gottfried Beer

Inventor： Rainer Steiner ,  Jens Pohl ,  Werner Robl ,  Gottfried Beer

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L24/03 ,  H01L23/3114 ,  H01L24/05 ,  H01L24/96 ,  H01L2224/0332 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/04105 ,  H01L2224/05001 ,  H01L2224/05082 ,  H01L2224/05546 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01068 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/18162 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor chip includes a contact pad on a main surface of the chip. An electrically conductive layer is applied onto the contact pad. The main surface of the semiconductor chip is covered with an insulating layer. An electrically conductive contact area is formed within the insulating layer such that the contact area and the insulating layer include coplanar exposed surfaces and the contact area is electrically connected with the electrically conductive layer and includes an extension which is greater than the extension of the electrically conductive layer along a direction parallel to the main surface of the semiconductor chip.

Abstract translation: 半导体芯片包括在芯片的主表面上的接触焊盘。 将导电层施加到接触垫上。 半导体芯片的主表面被绝缘层覆盖。 导电接触区域形成在绝缘层内，使得接触区域和绝缘层包括共面的暴露表面，并且接触区域与导电层电连接，并且包括延伸部，其延伸大于导电 层沿着与半导体芯片的主表面平行的方向。

公开(公告)号：US07807506B2

公开(公告)日：2010-10-05

申请号：US11701044

申请日：2007-02-01

Applicant: Gottfried Beer ,  Horst Theuss

Inventor： Gottfried Beer ,  Horst Theuss

IPC: H01L21/00

CPC classification number: B81C1/00269 ,  B81C2203/0118 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05099

Abstract: One aspect of the invention relates to a semiconductor component with cavity structure and a method for producing the same. The semiconductor component has an active semiconductor chip with the microelectromechanical structure and a wiring structure on its top side. The microelectromechanical structure is surrounded by walls of at least one cavity. A covering, which covers the cavity, is arranged on the walls. The walls have a photolithographically patterned polymer. The covering has a layer with a polymer of identical type. In one case, the molecular chains of the polymer of the walls are crosslinked with the molecular chains of the polymer layer of the covering layer to form a dimensionally stable cavity housing.

Abstract translation: 本发明的一个方面涉及具有腔结构的半导体部件及其制造方法。 半导体部件具有微机电结构的有源半导体芯片及其顶侧的布线结构。 微机电结构由至少一个空腔的壁包围。 覆盖空腔的覆盖物布置在墙壁上。 墙壁具有光刻图案的聚合物。 覆盖物具有具有相同类型的聚合物的层。 在一种情况下，壁的聚合物的分子链与覆盖层的聚合物层的分子链交联，以形成尺寸稳定的腔体。

公开(公告)号：US20100207272A1

公开(公告)日：2010-08-19

申请号：US12389103

申请日：2009-02-19

Applicant: Rainer Steiner ,  Jens Pohl ,  Werner Robl ,  Markus Brunnbauer ,  Gottfried Beer

Inventor： Rainer Steiner ,  Jens Pohl ,  Werner Robl ,  Markus Brunnbauer ,  Gottfried Beer

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/561 ,  H01L21/568 ,  H01L23/5283 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/02351 ,  H01L2224/03462 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05006 ,  H01L2224/05012 ,  H01L2224/05017 ,  H01L2224/05546 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/00

Abstract: A semiconductor device includes a chip comprising a contact element, a structured dielectric layer over the chip, and a conductive element coupled to the contact element. The conductive element comprises a first portion embedded in the structured dielectric layer, a second portion at least partially spaced apart from the first portion and embedded in the structured dielectric layer, and a third portion contacting a top of the structured dielectric layer and extending at least vertically over the first portion and the second portion.

Abstract translation: 半导体器件包括芯片，其包括接触元件，芯片上方的结构化介电层以及耦合到接触元件的导电元件。 导电元件包括​​嵌入结构化电介质层中的第一部分，与第一部分至少部分间隔开并嵌入结构化介电层的第二部分，以及接触结构化介电层顶部并至少延伸的第三部分 垂直于第一部分和第二部分。

公开(公告)号：US20100062563A1

公开(公告)日：2010-03-11

申请号：US12205294

申请日：2008-09-05

Applicant: Klaus Pressel ,  Gottfried Beer

Inventor： Klaus Pressel ,  Gottfried Beer

IPC: H01L21/50

CPC classification number: H01L21/6835 ,  H01L21/568 ,  H01L23/3107 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/32145 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06593 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/82 ,  H01L2924/00

Abstract: A method of manufacturing a stacked die module includes applying a plurality of stacked die structures to a carrier. Each stacked die structure includes a first semiconductor die applied to the carrier and a second semiconductor die stacked over the first semiconductor die. The second semiconductor die has a larger lateral surface area than the first semiconductor die. A dam is applied around each of the stacked die structures, thereby forming an enclosed cavity for each of the stacked die structures. The enclosed cavity for each stacked die structure surrounds the first semiconductor die of the stacked die structure.

Abstract translation: 制造堆叠模具模块的方法包括将多个堆叠的模具结构应用于载体。 每个堆叠的管芯结构包括施加到载体的第一半导体管芯和堆叠在第一半导体管芯上的第二半导体管芯。 第二半导体管芯具有比第一半导体管芯更大的侧表面积。 在每个堆叠的模具结构周围施加坝，从而为每个堆叠的模具结构形成封闭的腔。 用于每个堆叠的管芯结构的封闭空腔包围堆叠管芯结构的第一半导体管芯。