公开(公告)号：US08110415B2

公开(公告)日：2012-02-07

申请号：US12062055

申请日：2008-04-03

申请人： John Ulrich Knickerbocker ,  John H. Magerlein

发明人： John Ulrich Knickerbocker ,  John H. Magerlein

IPC分类号： H01L21/66

CPC分类号： H01L23/34 ,  G01R31/2877 ,  H01L23/473 ,  H01L23/5384 ,  H01L23/544 ,  H01L25/0652 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00

摘要： A chip package includes: a substrate; a plurality of conductive connections in contact with the silicon carrier; a silicon carrier in a prefabricated shape disposed above the substrate, the silicon carrier including: a plurality of through silicon vias for providing interconnections through the silicon carrier to the chip; liquid microchannels for cooling; a liquid coolant flowing through the microchannels; and an interconnect to one or more chips or chip stacks.

摘要翻译： 芯片封装包括：基板; 与硅载体接触的多个导电连接; 设置在所述衬底上方的预制形状的硅载体，所述硅载体包括：多个通过硅通孔，用于提供通过所述硅载体与所述芯片的互连; 液体微通道进行冷却; 流过微通道的液体冷却剂; 以及与一个或多个芯片或芯片堆叠的互连。

公开(公告)号：US07892885B2

公开(公告)日：2011-02-22

申请号：US11929335

申请日：2007-10-30

申请人： Alain Caron ,  John Ulrich Knickerbocker

发明人： Alain Caron ,  John Ulrich Knickerbocker

IPC分类号： H01L21/58

CPC分类号： H01L23/5385 ,  H01L21/486 ,  H01L23/5384 ,  H01L23/60 ,  H01L24/16 ,  H01L25/0652 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2224/48

摘要： Techniques for modular chip fabrication are provided. In one aspect, a modular chip structure is provided. The modular chip structure comprises a substrate; a carrier platform attached to the substrate, the carrier platform comprising a plurality of conductive vias extending through the carrier platform; and a wiring layer on the carrier platform in contact with one or more of the conductive vias, wherein the wiring layer comprises one or more wiring levels and is configured to divide the carrier platform into a plurality of voltage islands; and chips, chip macros or at least one chip in combination with at least one chip macro assembled on the carrier platform.

摘要翻译： 提供了模块化芯片制造技术。 一方面，提供了一种模块化芯片结构。 模块化芯片结构包括基板; 载体平台，其附接到所述基底，所述载体平台包括延伸穿过所述载体平台的多个导电通孔; 以及载体平台上的一个或多个导电通孔接触的布线层，其中所述布线层包括一个或多个布线层，并且被配置为将所述载体平台划分成多个电压岛; 芯片，芯片宏或至少一个芯片组合在载体平台上组装的至少一个芯片宏。

公开(公告)号：US07808798B2

公开(公告)日：2010-10-05

申请号：US12062665

申请日：2008-04-04

申请人： John Michael Cotte ,  Brian Paul Gaucher ,  Janusz Grzyb ,  Nils Deneke Hoivik ,  Christopher Vincent Jahnes ,  John Ulrich Knickerbocker ,  Duixian Liu ,  John Harold Magerlein ,  Chirag Suryakant Patel ,  Ullrich R. Pfeiffer ,  Cornelia Kang-I Tsang

发明人： John Michael Cotte ,  Brian Paul Gaucher ,  Janusz Grzyb ,  Nils Deneke Hoivik ,  Christopher Vincent Jahnes ,  John Ulrich Knickerbocker ,  Duixian Liu ,  John Harold Magerlein ,  Chirag Suryakant Patel ,  Ullrich R. Pfeiffer ,  Cornelia Kang-I Tsang

IPC分类号： H05K1/18

CPC分类号： H01L25/165 ,  H01L23/66 ,  H01L24/24 ,  H01L24/82 ,  H01L25/162 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/24227 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01Q1/2283 ,  H01L2924/00 ,  H01L2224/0401

摘要： An apparatus is described incorporating an interposer having a cavity for a portion of an antenna structure, having conductor through vias, a top Si part having interconnection wiring and having pads for electrically mounting an integrated circuit chip thereon, wherein the top Si part mates with the interposer electrically and mechanically. The interposer and top Si part may be scaled to provide an array of functional units. The invention overcomes the problem of combining a high efficient antenna with integrated circuit chips in a Si package with signal frequencies from 1 to 100 GHz and the problem of shielding components proximate to the antenna and reduces strain arising from mismatching of TCEs.

摘要翻译： 描述了一种装置，其具有用于天线结构的一部分的空腔的插入件，具有导体穿过通孔，顶部Si部分具有互连布线并具有用于在其上电气安装集成电路芯片的焊盘，其中顶部Si部分与 内插器电气和机械。 插入器和顶部Si部分可以被缩放以提供功能单元的阵列。 本发明克服了将高效天线与Si封装中的集成电路芯片组合在一起的信号频率为1至100GHz的问题，以及屏蔽靠近天线的组件的问题，并减少了由于TCE失配引起的应变。

公开(公告)号：US07741153B2

公开(公告)日：2010-06-22

申请号：US11929612

申请日：2007-10-30

申请人： Alain Caron ,  John Ulrich Knickerbocker

发明人： Alain Caron ,  John Ulrich Knickerbocker

IPC分类号： H01L21/00

CPC分类号： H01L25/0652 ,  H01L23/49827 ,  H01L23/60 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/8185 ,  H01L2224/81895 ,  H01L2224/831 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2224/48

摘要： Modular chip integration and operation techniques are provided. In one aspect, a method of integrating chips, chip macros or at least one chip in combination with at least one chip macro is provided. The method comprises the following steps. The chips, chip macros or at least one chip in combination with at least one chip macro are assembled on a single carrier platform. One or more signal inputs and outputs are provided to each of the chips, chip macros or at least one chip in combination with at least one chip macro. One or more power and ground inputs and outputs are provided to each of the chips, chip macros or at least one chip in combination with at least one chip macro. The power and ground inputs and outputs to one or more of the chips, chip macros or at least one chip in combination with at least one chip macro are segmented from the power and ground inputs and outputs to at least one other of the chips, chip macros or at least one chip in combination with at least one chip macro so as to form a plurality of voltage islands.

摘要翻译： 提供了模块化芯片集成和操作技术。 一方面，提供将芯片，芯片宏或至少一个芯片与至少一个芯片宏组合的方法。 该方法包括以下步骤。 将芯片，芯片宏或至少一个与至少一个芯片宏组合的芯片组装在单个载体平台上。 每个芯片，芯片宏或至少一个芯片与至少一个芯片宏组合提供一个或多个信号输入和输出。 一个或多个电源和接地输入和输出被提供给每个芯片，芯片宏或至少一个芯片与至少一个芯片宏组合。 电源和接地输入和输出到一个或多个芯片，芯片宏或至少一个芯片与至少一个芯片宏的组合被分割成电源和地面输入并输出到至少另一个芯片，芯片 宏或至少一个芯片与至少一个芯片宏组合，以便形成多个电压岛。

公开(公告)号：US07713575B2

公开(公告)日：2010-05-11

申请号：US11396107

申请日：2006-03-31

申请人： Peter A. Gruber ,  John Ulrich Knickerbocker

发明人： Peter A. Gruber ,  John Ulrich Knickerbocker

IPC分类号： B05D5/12

CPC分类号： H05K3/3457 ,  H01L21/288 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/11009 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/1319 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H05K2203/0113 ,  H05K2203/0557 ,  H01L2924/00

摘要： A method and apparatus for the formation of coplanar electrical interconnectors. Solder material is deposited onto a wafer, substrate, or other component of an electrical package using a complaint mold such that the terminal ends of the solder material being deposited, i.e., the ends opposite to those forming an attachment to the wafer, substrate, or other component of an electrical package are coplanar with one another. A complaint mold is used having one or more conduits for receiving solder material and having a compliant side and a planar side. The compliant side of the mold is positioned adjacent to the wafer, substrate, or other component of an electrical package allowing solder material to be deposited onto the surface thereof such that the planar side of the compliant mold provides coplanar interconnectors. An Injection Molded Solder (IMS) head can be used as the means for filling the conduits of the compliant mold of the present invention.

摘要翻译： 用于形成共面电连接器的方法和装置。 使用投诉模具将焊料沉积到电气封装的晶片，基板或其它部件上，使得焊料材料的末端被沉积，即与形成与晶片，基板或附件形成连接的端部相对的端部 电气封装的其他部件彼此共面。 使用投诉模具具有一个或多个用于接收焊料材料并具有柔性侧面和平面侧的导管。 模具的柔性侧被定位成与电气封装的晶片，衬底或其它部件相邻，允许将焊料材料沉积到其表面上，使得柔性模具的平面侧提供共面的互连器件。 可以使用注射成型焊料（IMS）头作为填充本​​发明的柔性模具的导管的装置。

公开(公告)号：US20090308308A1

公开(公告)日：2009-12-17

申请号：US12544345

申请日：2009-08-20

申请人： Peter A. Gruber ,  John Ulrich Knickerbocker

发明人： Peter A. Gruber ,  John Ulrich Knickerbocker

IPC分类号： B05C1/00

CPC分类号： H05K3/3457 ,  H01L21/288 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/11009 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/1319 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H05K2203/0113 ,  H05K2203/0557 ,  H01L2924/00

摘要： A method and apparatus for the formation of coplanar electrical interconnectors. Solder material is deposited onto a wafer, substrate, or other component of an electrical package using a complaint mold such that the terminal ends of the solder material being deposited, i.e., the ends opposite to those forming an attachment to the wafer, substrate, or other component of an electrical package are coplanar with one another. A complaint mold is used having one or more conduits for receiving solder material and having a compliant side and a planar side. The compliant side of the mold is positioned adjacent to the wafer, substrate, or other component of an electrical package allowing solder material to be deposited onto the surface thereof such that the planar side of the compliant mold provides coplanar interconnectors. An Injection Molded Solder (IMS) head can be used as the means for filling the conduits of the compliant mold of the present invention.

摘要翻译： 用于形成共面电连接器的方法和装置。 使用投诉模具将焊料沉积到电气封装的晶片，基板或其他部件上，使得焊料材料的末端被沉积，即与形成与晶片，基板或附件形成连接的端部相对的端部 电气封装的其他部件彼此共面。 使用投诉模具具有一个或多个用于接收焊料材料并具有柔性侧面和平面侧的导管。 模具的柔性侧被定位成与电气封装的晶片，衬底或其它部件相邻，允许将焊料材料沉积到其表面上，使得柔性模具的平面侧提供共面的互连器件。 可以使用注射成型焊料（IMS）头作为填充本​​发明的柔性模具的导管的装置。

公开(公告)号：US07615405B2

公开(公告)日：2009-11-10

申请号：US11872331

申请日：2007-10-15

申请人： Paul Stephen Andry ,  Leena Paivikki Buchwalter ,  Raymond R. Horton ,  John Ulrich Knickerbocker ,  Cornelia K. Tsang ,  Steven Lorenz Wright

发明人： Paul Stephen Andry ,  Leena Paivikki Buchwalter ,  Raymond R. Horton ,  John Ulrich Knickerbocker ,  Cornelia K. Tsang ,  Steven Lorenz Wright

IPC分类号： H01L21/50 ,  H01L21/48 ,  H01L21/44

CPC分类号： H01L24/81 ,  H01L23/544 ,  H01L24/48 ,  H01L24/97 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/48227 ,  H01L2224/81001 ,  H01L2224/81054 ,  H01L2224/81136 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15157 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/20109 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An electronic dive and method of fabricating an electronic device. The method including placing a placement guide over a top surface of a module substrate, the placement guide having a guide opening, the guide opening extending from a top surface of the placement guide to a bottom surface of the placement guide; aligning the placement guide to an integrated circuit chip position on the module substrate; fixing the placement guide to the module substrate; placing an integrated circuit chip in the guide opening, sidewalls of the placement guide opening constraining electrically conductive bonding structures on bottom surface of the integrated circuit chip to self-align to an electrically conductive module substrate contact pad on the top surface of the module substrate in the integrated circuit chip position; and bonding the bonding structures to the module substrate contact pads, the bonding structures and the module substrate contact pads in direct physical and electrical contact after the bonding.

摘要翻译： 一种电子潜水及其制造方法。 所述方法包括将放置引导件放置在模块基板的顶表面上，所述放置引导件具有引导开口，所述引导开口从所述放置引导件的顶表面延伸到所述放置引导件的底表面; 将所述放置引导件对准所述模块基板上的集成电路芯片位置; 将所述放置引导件固定到所述模块基板; 将集成电路芯片放置在引导开口中，放置引导开口的侧壁约束集成电路芯片的底表面上的导电接合结构，以与模块基板的顶表面上的导电模块衬底接触焊盘自对准 集成电路芯片位置; 以及在接合之后将结合结构粘合到模块衬底接触焊盘，接合结构和模块衬底接触焊盘，直接物理和电接触。

公开(公告)号：US20090251862A1

公开(公告)日：2009-10-08

申请号：US12062055

申请日：2008-04-03

申请人： John Ulrich Knickerbocker ,  John H. Magerlein

发明人： John Ulrich Knickerbocker ,  John H. Magerlein

IPC分类号： H05K7/20 ,  H01L21/66

CPC分类号： H01L23/34 ,  G01R31/2877 ,  H01L23/473 ,  H01L23/5384 ,  H01L23/544 ,  H01L25/0652 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00

摘要： A chip package includes: a substrate; a plurality of conductive connections in contact with the silicon carrier; a silicon carrier in a prefabricated shape disposed above the substrate, the silicon carrier including: a plurality of through silicon vias for providing interconnections through the silicon carrier to the chip; liquid microchannels for cooling; a liquid coolant flowing through the microchannels; and an interconnect to one or more chips or chip stacks.

摘要翻译： 芯片封装包括：基板; 与硅载体接触的多个导电连接; 设置在所述衬底上方的预制形状的硅载体，所述硅载体包括：多个通过硅通孔，用于提供通过所述硅载体与所述芯片的互连; 液体微通道进行冷却; 流过微通道的液体冷却剂; 以及与一个或多个芯片或芯片堆叠的互连。

公开(公告)号：US20090108427A1

公开(公告)日：2009-04-30

申请号：US11929335

申请日：2007-10-30

申请人： Alain Caron ,  John Ulrich Knickerbocker

发明人： Alain Caron ,  John Ulrich Knickerbocker

IPC分类号： H01L23/12 ,  H01L21/58

CPC分类号： H01L23/5385 ,  H01L21/486 ,  H01L23/5384 ,  H01L23/60 ,  H01L24/16 ,  H01L25/0652 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2224/48

摘要： Techniques for modular chip fabrication are provided. In one aspect, a modular chip structure is provided. The modular chip structure comprises a substrate; a carrier platform attached to the substrate, the carrier platform comprising a plurality of conductive vias extending through the carrier platform; and a wiring layer on the carrier platform in contact with one or more of the conductive vias, wherein the wiring layer comprises one or more wiring levels and is configured to divide the carrier platform into a plurality of voltage islands; and chips, chip macros or at least one chip in combination with at least one chip macro assembled on the carrier platform.

摘要翻译： 提供了模块化芯片制造技术。 一方面，提供了一种模块化芯片结构。 模块化芯片结构包括基板; 载体平台，其附接到所述基底，所述载体平台包括延伸穿过所述载体平台的多个导电通孔; 以及载体平台上的一个或多个导电通孔接触的布线层，其中所述布线层包括一个或多个布线层，并且被配置为将所述载体平台划分成多个电压岛; 芯片，芯片宏或至少一个芯片组合在载体平台上组装的至少一个芯片宏。

公开(公告)号：US07514290B1

公开(公告)日：2009-04-07

申请号：US12108512

申请日：2008-04-24

申请人： Katsuyuki Sakuma ,  Paul Stephen Andry ,  Kuniaki Sueoka ,  John Ulrich Knickerbocker

发明人： Katsuyuki Sakuma ,  Paul Stephen Andry ,  Kuniaki Sueoka ,  John Ulrich Knickerbocker

IPC分类号： H01L21/00

CPC分类号： H01L25/50 ,  H01L24/80 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/09701

摘要： This embodiment addresses a novel Chip-to-wafer chip lamination technique that provides low cost and high throughput. In the Chip-to-Chip process, using the temperature rise and utilizing deformation caused by thermal expansion of a metal shim inserted between the inner wall of a cavity, in which multiple chips are laminated and accommodated, multiple chips in the cavity are pressed against a reference surface on a side wall of the cavity to automatically perform positioning.

摘要翻译： 本实施例解决了提供低成本和高吞吐量的新型芯片到晶片芯片层叠技术。 在芯片到芯片工艺中，使用温度升高并且利用插入在空腔的内壁之间的金属垫片的热膨胀引起的变形，其中多个芯片被层压和容纳在腔体中的多个芯片被压靠 空腔侧壁上的参考表面，以自动执行定位。