公开(公告)号：US20190035897A1

公开(公告)日：2019-01-31

申请号：US16072313

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Chandra S. MOHAPATRA ,  Harold W. KENNEL ,  Glenn A. GLASS ,  Will RACHMADY ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Anand S. MURTHY ,  Tahir GHANI ,  Matthew V. METZ ,  Sean T. MA

IPC: H01L29/205 ,  H01L29/66 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/205 ,  H01L27/0924 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: An apparatus including a transistor device on a substrate including an intrinsic layer including a channel; a source and a drain on opposite sides of the channel; and a diffusion barrier between the intrinsic layer and each of the source and the drain, the diffusion barrier including a conduction band energy that is less than a conduction band energy of the channel and greater than a material of the source and drain. A method including defining an area of an intrinsic layer on a substrate for a channel of a transistor device; forming a diffusion barrier layer in an area defined for a source and a drain; and forming a source on the diffusion barrier layer in the area defined for the source and forming a drain in the area defined for the drain.

公开(公告)号：US20180374940A1

公开(公告)日：2018-12-27

申请号：US16110458

申请日：2018-08-23

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Marko RADOSAVLJEVIC ,  Ravi PILLARISETTY ,  Matthew V. METZ

IPC: H01L29/775 ,  H01L29/786 ,  H01L29/49 ,  H01L29/423 ,  H01L29/205 ,  H01L29/15 ,  B82Y10/00 ,  H01L29/66 ,  H01L29/51 ,  B82Y40/00 ,  H01L29/06

CPC classification number: H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/155 ,  H01L29/205 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66469 ,  H01L29/78681 ,  H01L29/78696

Abstract: Semiconductor devices having group III-V material active regions and graded gate dielectrics and methods of fabricating such devices are described. In an example, a semiconductor device includes a group III-V material channel region disposed above a substrate. A gate stack is disposed on the group III-V material channel region. The gate stack includes a graded high-k gate dielectric layer disposed directly between the III-V material channel region and a gate electrode. The graded high-k gate dielectric layer has a lower dielectric constant proximate the III-V material channel region and has a higher dielectric constant proximate the gate electrode. Source/drain regions are disposed on either side of the gate stack.

公开(公告)号：US20170256408A1

公开(公告)日：2017-09-07

申请号：US15604550

申请日：2017-05-24

Applicant: Intel Corporation

Inventor： Niloy MUKHERJEE ,  Niti GOEL ,  Sanaz K. GARDNER ,  Pragyansri PATHI ,  Matthew V. METZ ,  Sansaptak DASGUPTA ,  Seung Hoon SUNG ,  James M. POWERS ,  Gilbert DEWEY ,  Benjamin CHU-KUNG ,  Jack T. KAVALIEROS ,  Robert S. CHAU

IPC: G06Q30/02

CPC classification number: H01L21/02694 ,  H01L21/02381 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02609 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8258 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/7848

Abstract: Trenches (and processes for forming the trenches) are provided that reduce or prevent crystaline defects in selective epitaxial growth of type III-V or Germanium (Ge) material (e.g., a “buffer” material) from a top surface of a substrate material. The defects may result from collision of selective epitaxial sidewall growth with oxide trench sidewalls. Such trenches include (1) a trench having sloped sidewalls at an angle of between 40 degrees and 70 degrees (e.g., such as 55 degrees) with respect to a substrate surface; and/or (2) a combined trench having an upper trench over and surrounding the opening of a lower trench (e.g., the lower trench may have the sloped sidewalls, short vertical walls, or tall vertical walls). These trenches reduce or prevent defects in the epitaxial sidewall growth where the growth touches or grows against vertical sidewalls of a trench it is grown in.

公开(公告)号：US20170186598A1

公开(公告)日：2017-06-29

申请号：US15458897

申请日：2017-03-14

Applicant: Intel Corporation

Inventor： Niti Goel ,  Robert S. CHAU ,  Jack T. KAVALIEROS ,  Benjamin CHU-KUNG ,  Matthew V. METZ ,  Niloy MUKHERJEE ,  Nancy M. ZELICK ,  Gilbert DEWEY ,  Willy RACHMADY ,  Marko RADOSAVLJEVIC ,  Van H. LE ,  Ravi PILLARISETTY ,  Sansaptak DASGUPTA

IPC: H01L21/02 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/16 ,  H01L29/20 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L21/0245 ,  H01L21/02381 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02598 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8252 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66795 ,  H01L29/785

Abstract: A single fin or a pair of co-integrated n- and p-type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.

公开(公告)号：US20160181099A1

公开(公告)日：2016-06-23

申请号：US14908987

申请日：2013-09-04

Applicant: INTEL CORPORATION

Inventor： Niloy MUKHERJEE ,  Niti GOEL ,  Sanaz K. GARDNER ,  Pragyansri PATHI ,  Matthew V. METZ ,  Sansaptak DASGUPTA ,  Seung Hoon SUNG ,  James M. POWERS ,  Gilbert DEWEY ,  Benjamin CHU-KUNG ,  Jack T. KAVALIEROS ,  Robert S. CHAU

IPC: H01L21/02 ,  H01L27/092 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165 ,  H01L29/04 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/267

CPC classification number: H01L21/02694 ,  H01L21/02381 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02609 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8258 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/7848

Abstract: Trenches (and processes for forming the trenches) are provided that reduce or prevent crystaline defects in selective epitaxial growth of type III-V or Germanium (Ge) material (e.g., a “buffer” material) from a top surface of a substrate material. The defects may result from collision of selective epitaxial sidewall growth with oxide trench sidewalls. Such trenches include (I) a trench having sloped sidewalls at an angle of between 40 degrees and 70 degrees (e.g., such as 55 degrees) with respect to a substrate surface; and/or (2) a combined trench having an upper trench over and surrounding the opening of a lower trench (e.g., the lower trench may have the sloped sidewalls, short vertical walls, or tall vertical walls). These trenches reduce or prevent defects in the epitaxial sidewall growth where the growth touches or grows against vertical sidewalls of a trench it is grown in.

Abstract translation: 提供沟槽（以及用于形成沟槽的工艺），其从衬底材料的顶表面减少或防止III-V族或锗（Ge）材料（例如，“缓冲材料”）的选择性外延生长中的晶体缺陷。 缺陷可能由选择性外延侧壁生长与氧化物沟槽侧壁的碰撞引起。 这种沟槽包括（I）相对于衬底表面以40度至70度（例如55度）之间的角度具有倾斜侧壁的沟槽; 和/或（2）具有在下沟槽的开口上方并且围绕下沟槽（例如，下沟槽可以具有倾斜侧壁，短垂直壁或高垂直壁）的上沟槽的组合沟槽。 这些沟槽减少或防止外延侧壁生长中的缺陷，其中生长与其生长的沟槽的垂直侧壁接触或生长。

公开(公告)号：US20230411443A1

公开(公告)日：2023-12-21

申请号：US18129258

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Kaan OGUZ ,  Chia-Ching LIN ,  Arnab SEN GUPTA ,  I-Cheng TUNG ,  Sou-Chi CHANG ,  Sudarat LEE ,  Matthew V. METZ ,  Uygar E. AVCI ,  Scott B. CLENDENNING ,  Ian A. YOUNG

IPC: H01L21/02 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L28/56 ,  H01L28/92 ,  H01L28/91 ,  H01L28/75 ,  H01L23/5223 ,  H01L23/5226 ,  H01L24/32 ,  H01L28/65 ,  H01L2224/32225 ,  H01L24/73 ,  H01L2224/16227 ,  H01L24/16 ,  H01L2224/73204

Abstract: Metal insulator metal capacitors are described. In an example, a metal-insulator-metal (MIM) capacitor includes a first electrode. An insulator is over the first electrode. The insulator includes a first layer, and a second layer over the first layer. The first layer has a leakage current that is less than a leakage current of the second layer. The second layer has a dielectric constant that is greater than a dielectric constant of the first layer. A second electrode is over the insulator.

公开(公告)号：US20230100505A1

公开(公告)日：2023-03-30

申请号：US17485238

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Ashish Verma PENUMATCHA ,  Sarah ATANASOV ,  Seung Hoon SUNG ,  Rahul RAMAMURTHY ,  I-Cheng TUNG ,  Uygar E. AVCI ,  Matthew V. METZ ,  Jack T. KAVALIEROS ,  Chia-Ching LIN ,  Kaan OGUZ

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/66

Abstract: Embodiments disclosed herein include transistor devices and methods of forming such devices. In an embodiment, a transistor device comprises a first channel, wherein the first channel comprises a semiconductor material and a second channel above the first channel, wherein the second channel comprises the semiconductor material. In an embodiment, a first spacer is between the first channel and the second channel, and a second spacer is between the first channel and the second channel. In an embodiment, a first gate dielectric is over a surface of the first channel that faces the second channel, and a second gate dielectric is over a surface of the second channel that faces the first channel. In an embodiment, the first gate dielectric is physically separated from the second gate dielectric.

公开(公告)号：US20230098594A1

公开(公告)日：2023-03-30

申请号：US17484949

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Chia-Ching LIN ,  Kaan OGUZ ,  Sou-Chi CHANG ,  Arnab SEN GUPTA ,  I-Cheng TUNG ,  Ian A. YOUNG ,  Matthew V. METZ ,  Uygar E. AVCI ,  Sudarat LEE

IPC: H01G4/30 ,  H01L49/02 ,  H01G4/08 ,  H01G4/35

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related MIM capacitors that have a multiple trench structure to increase a charge density, where a dielectric of the MIM capacitor includes a perovskite-based material. In embodiments, a first electrically conductive layer may be coupled with a top metal layer of the MIM, and/or a second conductive layer may be coupled with a bottom metal layer of the MIM to reduce RC effects. Other embodiments may be described and/or claimed.

公开(公告)号：US20220199839A1

公开(公告)日：2022-06-23

申请号：US17133599

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Arnab SEN GUPTA ,  Urusa ALAAN ,  Justin WEBER ,  Charles C. KUO ,  Yu-Jin CHEN ,  Kaan OGUZ ,  Matthew V. METZ ,  Abhishek A. SHARMA ,  Prashant MAJHI ,  Brian S. DOYLE ,  Van H. LE

IPC: H01L29/872 ,  H01L27/07 ,  H01L29/47 ,  H01L29/22

Abstract: Embodiments disclosed herein include semiconductor devices with Schottky diodes in a back end of line stack. In an embodiment, a semiconductor device comprises a semiconductor layer, where transistor devices are provided in the semiconductor layer, and a back end stack over the semiconductor layer. In an embodiment, a diode is in the back end stack. In an embodiment, the diode comprises a first electrode, a semiconductor region over the first electrode, and a second electrode over the semiconductor region. In an embodiment, a first interface between the first electrode and the semiconductor region is an ohmic contact, and a second interface between the semiconductor region and the second electrode is a Schottky contact.

公开(公告)号：US20220199756A1

公开(公告)日：2022-06-23

申请号：US17133105

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： I-Cheng TUNG ,  Kaan OGUZ ,  Chia-Ching LIN ,  Sou-Chi CHANG ,  Matthew V. METZ ,  Uygar E. AVCI

IPC: H01L49/02 ,  H01L23/522 ,  H01L29/24 ,  H01L29/786 ,  H01L29/66

Abstract: Metal insulator metal capacitors or backend transistors having epitaxial oxides are described. In a first example, metal-insulator-metal (MIM) capacitor includes a first electrode plate. A capacitor dielectric is on the first electrode plate. The capacitor dielectric includes a single crystalline oxide material. A second electrode plate is on the capacitor dielectric, the second electrode plate having a portion over and parallel with the first electrode plate. In a second example, a transistor includes a gate electrode above a substrate. A gate dielectric above and on the gate electrode. The gate dielectric includes a single crystalline oxide material. A channel material layer is on the single crystalline oxide material. Source or drain contacts are on the channel material layer.