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    Titanium-Based High-K Dielectric Films
    51.
    发明申请
    Titanium-Based High-K Dielectric Films 有权
    钛基高K介电薄膜

    公开(公告)号：US20130044404A1

    公开(公告)日：2013-02-21

    申请号：US13657782

    申请日：2012-10-22

    Applicant: Intermolecular, Inc.

    Inventor： Hanhong Chen ,  Nobumichi Fuchigami ,  Imran Hashim ,  Edward L. Haywood ,  Pragati KUMAR ,  Sandra G. Malhotra ,  Monica Sawkar Mathur ,  Prashant B. Phatak ,  Sunil Shanker

    IPC: H01G4/30 ,  H01G4/018

    CPC classification number: H01G4/1218 ,  C23C16/405 ,  C23C16/45531 ,  C23C16/56 ,  H01G4/33 ,  H01L21/02186 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02312 ,  H01L21/02337 ,  H01L21/3141 ,  H01L21/3142 ,  H01L28/40

    Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on titanium oxide, to suppress the formation of anatase-phase titanium oxide and (b) related devices and structures. A metal-insulator-metal (“MIM”) stack is formed using an ozone pretreatment process of a bottom electrode (or other substrate) followed by an ALD process to form a TiO2 dielectric, rooted in the use of an amide-containing precursor. Following the ALD process, an oxidizing anneal process is applied in a manner is hot enough to heal defects in the TiO2 dielectric and reduce interface states between TiO2 and electrode; the anneal temperature is selected so as to not be so hot as to disrupt BEL surface roughness. Further process variants may include doping the titanium oxide, pedestal heating during the ALD process to 275-300 degrees Celsius, use of platinum or ruthenium for the BEL, and plural reagent pulses of ozone for each ALD process cycle. The process provides high deposition rates, and the resulting MIM structure has substantially no x-ray diffraction peaks associated with anatase-phase titanium oxide.

    Abstract translation: 本公开内容提供（a）制造基于氧化钛的氧化物层（例如电介质层）的方法，以抑制锐钛矿相氧化钛的形成和（b）相关的器件和结构。 使用底部电极（或其他基底）的臭氧预处理随后进行ALD工艺形成金属 - 绝缘体 - 金属（MIM）堆叠，以形成使用含酰胺前体的TiO 2电介质。 在ALD工艺之后，氧化退火工艺的应用热度足以愈合TiO2电介质中的缺陷，并降低TiO2和电极之间的界面态; 选择退火温度以使其不那么热，以致破坏BEL表面粗糙度。 进一步的工艺变型可以包括在ALD工艺期间掺杂氧化钛，基座加热至275-300摄氏度，对于BEL使用铂或钌，对于每个ALD工艺循环使用多个试剂脉冲的臭氧。 该方法提供高沉积速率，并且所得MIM结构基本上没有与锐钛矿相氧化钛相关的x射线衍射峰。

    Current selector for non-volatile memory in a cross bar array based on defect and band engineering metal-dielectric-metal stacks
    53.
    发明授权
    Current selector for non-volatile memory in a cross bar array based on defect and band engineering metal-dielectric-metal stacks 有权
    基于缺陷和带工程金属 - 电介质金属叠层的交叉条阵列中的非易失性存储器的当前选择器

    公开(公告)号：US09397141B2

    公开(公告)日：2016-07-19

    申请号：US14294519

    申请日：2014-06-03

    Applicant: Intermolecular, Inc.

    Inventor： Imran Hashim ,  Venkat Ananthan ,  Tony P. Chiang ,  Prashant B. Phatak

    IPC: H01L45/00 ,  H01L47/00 ,  H01L27/24 ,  H01L29/872

    CPC classification number: H01L27/2418 ,  H01L27/2409 ,  H01L29/872 ,  H01L45/10

    Abstract: Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. In some embodiments, the selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a high leakage dielectric layer sandwiched between two lower leakage dielectric layers. The low leakage layers can function to restrict the current flow across the selector device at low voltages. The high leakage dielectric layer can function to enhance the current flow across the selector device at high voltages.

    Abstract translation: 可适用于存储器件应用的选择器器件可在低电压下具有低漏电流，以减少非选定器件的漏电流路径，以及高电压下的高泄漏电流，以最大限度地减少器件切换期间的电压降。 在一些实施例中，选择器装置可以包括第一电极，三层电介质层和第二电极。 三层电介质层可以包括夹在两个较低的漏电介质层之间的高泄漏电介质层。 低泄漏层可以起到限制低电压下选择器装置的电流的作用。 高泄漏电介质层可以用于在高电压下增强选择器装置上的电流。

    Method to Improve DRAM Performance
    55.
    发明申请
    Method to Improve DRAM Performance 审中-公开
    提高DRAM性能的方法

    公开(公告)号：US20160093625A1

    公开(公告)日：2016-03-31

    申请号：US14502728

    申请日：2014-09-30

    Applicant: Intermolecular, Inc.

    Inventor： Xiangxin Rui ,  Imran Hashim ,  Prashant B. Phatak

    IPC: H01L27/108 ,  H01L49/02

    CPC classification number: H01L28/75 ,  H01L27/1085 ,  H01L28/55

    Abstract: A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive base layer and conductive metal oxide layer. The dielectric layer may include zirconium oxide or doped zirconium oxide. In some embodiments, the conductive metal oxide layer includes niobium oxide.

    Abstract translation: 形成金属绝缘体金属（MIM）DRAM电容器的第一电极层，其中第一电极层包含导电基底层和导电金属氧化物层。 电介质层可以包括氧化锆或掺杂氧化锆。 在一些实施例中，导电金属氧化物层包括氧化铌。

    ZrO-based high K dielectric stack for logic decoupling capacitor or embedded DRAM
    59.
    发明授权
    ZrO-based high K dielectric stack for logic decoupling capacitor or embedded DRAM 有权
    用于逻辑去耦电容器或嵌入式DRAM的基于ZrO的高K电介质堆叠

    公开(公告)号：US09099430B2

    公开(公告)日：2015-08-04

    申请号：US14135491

    申请日：2013-12-19

    Applicant: Intermolecular, Inc.

    Inventor： Imran Hashim ,  Xiangxin Rui

    IPC: H01L21/02 ,  H01L49/02 ,  H01L27/108

    CPC classification number: H01L28/40 ,  H01L27/10805

    Abstract: A zirconium oxide based dielectric material is used in the formation of decoupling capacitors employed in microelectronic logic circuits. In some embodiments, the zirconium oxide based dielectric is doped. In some embodiments, the dopant includes at least one of aluminum, silicon, or yttrium. In some embodiments, the zirconium oxide based dielectric is formed as a nanolaminate of zirconium oxide and a dopant metal oxide.

    Abstract translation: 在形成用于微电子逻辑电路中的去耦电容器中使用基于氧化锆的电介质材料。 在一些实施方案中，掺杂氧化锆基电介质。 在一些实施方案中，掺杂剂包括铝，硅或钇中的至少一种。 在一些实施方案中，基于氧化锆的电介质形成为氧化锆和掺杂剂金属氧化物的纳米氨酸盐。

    Transition Metal Oxide Bilayers
    60.
    发明申请
    Transition Metal Oxide Bilayers 有权
    过渡金属氧化物双层

    公开(公告)号：US20150200361A1

    公开(公告)日：2015-07-16

    申请号：US14618055

    申请日：2015-02-10

    Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

    Inventor： Hieu Pham ,  Vidyut Gopal ,  Imran Hashim ,  Tim Minvielle ,  Yun Wang ,  Takeshi Yamaguchi ,  Hong Sheng Yang

    IPC: H01L45/00

    CPC classification number: H01L45/08 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641

    Abstract: Embodiments of the invention include nonvolatile memory elements and memory devices comprising the nonvolatile memory elements. Methods for forming the nonvolatile memory elements are also disclosed. The nonvolatile memory element comprises a first electrode layer, a second electrode layer, and a plurality of layers of an oxide disposed between the first and second electrode layers. One of the oxide layers has linear resistance and substoichiometric composition, and the other oxide layer has bistable resistance and near-stoichiometric composition. Preferably, the sum of the two oxide layer thicknesses is between about 20 Å and about 100 Å, and the oxide layer with bistable resistance has a thickness between about 25% and about 75% of the total thickness. In one embodiment, the oxide layers are formed using reactive sputtering in an atmosphere with controlled flows of argon and oxygen.

    Abstract translation: 本发明的实施例包括非易失性存储器元件和包括非易失性存储元件的存储器件。 还公开了形成非易失性存储元件的方法。 非易失性存储元件包括第一电极层，第二电极层和设置在第一和第二电极层之间的多个氧化物层。 氧化物层中的一个具有线性电阻和亚化学计量组成，另一个氧化物层具有双稳态电阻和近化学计量组成。 优选地，两个氧化物层厚度的总和在约和之间，并且具有双稳态电阻的氧化物层具有在总厚度的约25％至约75％之间的厚度。 在一个实施例中，氧化物层在具有受控的氩气和氧气的气氛中使用反应溅射形成。

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